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參數(shù)資料
| 型號： | 935263293518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大小： | 324K |
| 代理商： | 935263293518 |
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Philips Semiconductors
Product specification
SC28L92
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
2000 Jan 21
21
The following named registers are the same for
Channels A and B
Mode Register
MRnA
MRnB
R/W
Status Register
SRA
SRB
R only
Clock Select
CSRA
CSRB
W only
Command Register
CRA
CRB
W only
Receiver FIFO
RxFIFOA
RxFIFOB
R only
Transmitter FIFO
TxFIFOA
TxFIFOB
W only
These are support functions for both Channels
Input Port Change Register
IPCR
R
Auxiliary Control Register
ACR
W
Interrupt Status Register
ISR
R
Interrupt Mask Register
IMR
W
Counter Timer Upper Value
CTU
R
Counter Timer Lower Value
CTL
R
Counter Timer Preset Upper
CTPU
W
Counter Timer Preset Lower
CTPL
W
Input Port Register
IPR
R
Output Configuration Register
OPCR
W
Set Output Port
Bits
W
Reset Output Port
Bits
W
Interrupt vector or GP register
IVR/GP
R/W
Table 2. Condensed Register bit formats
MR0 – MODE REGISTER 0
Bit 7
BIT 6
BIT 5BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
WATCHDOG
RxINT BIT 2
TxINT (1:0)
FIFO SIZE
BAUD RATE
EXTENDED II
TEST 2
BAUD RATE
EXTENDED 1
MR1 – MODE REGISTER 1
Bit 7
Bit 6
Bit 5
Bit 4:3
Bit 2
Bit 1:0
RxRTS Control
RxINT BIT 1
Error Mode
Parity Mode
Parity Type
Bits per Character
MR2 – MODE REGISTER 2
Bits 7:6
Bit 5
Bit 4
Bit 3:0
Channel Mode
TxRTS Control
CTSN Enable Tx
Stop Bit Length
CSR – CLOCK SELECT REGISTER
Bits 7:4
Bits 3:0
Receiver Clock,Select Code
Transmitter Clock select code,
CR –COMMAND REGISTER
Bits 7:4
Bit 3
Bit 2
Bit 1
Bit 0
Channel Command codes
Disable Tx
Enable Tx
Enable Tx
Enable Rx
SR – CHANNEL STATUS REGISTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Received Break
Framing Error
Parity Error
Overrun Error
TxEMT
TxRDY
RxFULL
RxRDY
IMR – INTERRUPT MASK REGISTER (ENABLES INTERRUPTS)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Change Input
Port
Change Break B
RxRDY B
TxRDTYB
Counter Ready
Change Break A
RxRDY A
TxRDY A
ISR – INTERRUPT STATUS REGISTER
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Change Input
Port
Change Break B
RxRDY B
TxRDTYB
Counter Ready
Change Break A
RxRDY A
TxRDY A
CTPU
– COUNTER TIMER PRESET REGISTERS, UPPER
Bits 7:0
8 MSB of the BRG Timer divisor.
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