參數(shù)資料
型號(hào)： 935262899118
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封裝： PLASTIC, TSSOP-16
文件頁(yè)數(shù)： 13/14頁(yè)
文件大?。?/td> 144K
代理商： 935262899118
Philips Semiconductors
Product specification
PCA9556
Octal SMBus Registered Interface
1998 Dec 18
8
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
VDD
Supply voltage
–0.5
+4.6
V
VI
Input voltage
VSS – 0.5
VDD + 0.5
V
II
DC input current
–
± 20
mA
VI/O
DC voltage on an I/O as an input other than I/O0
VSS – 0.5
VDD + 0.5
V
VI/O0
DC voltage on I/O0 as an input
VSS – 0.5
4.6
V
II/O0
DC input current on I/O0
–
+400
A
II/O0
DC in ut current on I/O0
–
–20
mA
II/O
DC output current on an I/O
–
± 20
mA
IDD
Supply current
–
mA
ISS
Supply current
–
mA
Ptot
Total power dissipation
–
mW
PO
Power dissipation per output
–
mW
Tstg
Storage temperature range
–65
+150
°C
Tamb
Operating ambient temperature
0
+70
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take
precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC24 under ”
Handling MOS devices”.
DC CHARACTERISTICS
VDD = 3.0 to 3.6 V; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Supplies
VDD
Supply voltage
3.0
3.6
V
IDD
Supply current
Operating mode; VDD = 3.3 V;
no load; VI = VDD or VSS;
fSCL = 100 kHz
300
425
A
Istb
Standby current
Standby mode; VDD = 3.3 V
no load; VI = VDD or VSS
25
50
A
VPOR
Power-on reset voltage
VDD = 3.3 V
no load; VI = VDD or VSS; note 1
1.3
2.4
V
input SCL; input/output SDA
VIL
LOW level input voltage
–0.5
0.8
V
VIH
HIGH level input voltage
2.1
VDD + 0.5
V
IOL
LOW level output current
VOL = 0.4V
3
–
mA
IL
Leakage current
VI = VDD = VSS
–1
+1
A
CI
Input capacitance
VI = VSS
–
10
pF
I/Os
VIL
LOW level input voltage
–0.5
–
0.8
V
VIH
HIGH level input voltage
2.0
–
VDD + 0.5
V
IIHL(max)
Maximum allowed input current through
protection diode (I/O1 – I/O7)
VI ≥ VDD or VI ≤ VSS
–
±400
A
IOL
LOW level output current
VOL = 0.55V; VDD = 3.3V
8
10
–
mA
HIGH level output current except I/O0
VOH = 2.4V; VDD = 3.3V
4
–
mA
IOH
HIGH level output current on I/O0
VDD = 3.6V; VOH = 4.6V
–
1
A
HIGH level out ut current on I/O0
VDD = 0V; VOH = 3.3V
–
1
A
IL
Input leakage current
VDD = 3.6V; VI = 0 or VDD
–1
1
A
CI
Input capacitance
–
10
pF
CO
Output capacitance
–
10
pF
Select Inputs A0, A1, A2, and RESET
VIL
LOW level input voltage
–0.5
0.8
V
VIH
HIGH level input voltage
2.0
VDD + 0.5
V
ILI
Input leakage current
–1
1
A
NOTE:
1. The power-on reset circuit resets the SMBus logic with VDD < VPOR and sets all I/Os to their default values
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