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參數(shù)資料
| 型號(hào)： | 935262731551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, LQFP-100 |
| 文件頁數(shù)： | 54/59頁 |
| 文件大?。?/td> | 383K |
| 代理商： | 935262731551 |
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Flow control using CTSN RTSN hardware handshaking
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Automatic address detection in multi-drop mode
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Three byte general purpose character recognition
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Fast data bus, 30 ns data bus release time, 125 ns bus cycle time
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Programmable interrupt priorities
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Automatic identification of highest priority interrupt pending
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Global interrupt and control registers ease setup and interrupt handling
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Vectored interrupts with programmable interrupt vector formats
- Interrupt vector modified with channel number
- Interrupt vector modified with channel number and channel type
- Interrupt vector not modified
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IACKN and DACKN signal pins
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Watch dog timer for each receiver (64 receive clock counts)
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Programmable Data Formats:
- 5 to 8 data bits plus parity
- Odd, even force or no parity
- 1, 1.5 or 2 stop bits
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Flexible baud rate selection for receivers and transmitters:
- 22 fixed rates; 50 - 230.4K baud or 100 to 460.8K baud
- Additional non–standard rates to 500K baud with internal generators
- Two reload-counters provide additional programmable baud rate generation
- External 1x or 16x clock inputs
- Simplified baud rate selection
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1 MHz 1x and 16x data rates full duplex all channels.
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Parity, framing and overrun error detection
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False start bit detection
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Line break detection and generation
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Programmable channel mode
- Normal(full duplex)
- Diagnostic modes
automatic echo
local loop back
emote loop back
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Four I/O ports per UART for modem controls, clocks, RTSN, I/O etc.
- All I/O ports equipped with ”Change of State Detectors”
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Two global inputs and two global outputs for general purpose I/O
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Power down mode
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On chip crystal oscillator, 2–8 MHz
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TTL input levels. Outputs switch between full V
CC and VSS
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High speed CMOS technology
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84 pin PLCC
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100 pin LQFP
Datasheet
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