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| 型號(hào)： | 935262731551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, LQFP-100 |
| 文件頁數(shù)： | 20/59頁 |
| 文件大?。?/td> | 383K |
| 代理商： | 935262731551 |
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Philips Semiconductors
Product specification
SC28L198
Octal UART for 3.3V and 5V supply voltage
1999 Jan 14
27
Table 22. XISR – Xon–Xoff Interrupt Status Register
Bits 7:6
Bits 5:4
Bits 3:2
Bits 1:0
Received X Character Sta-
tus
Automatic X Character transmis-
sion status
TxD flow status
TxD character status
00 – none
01 – Xoff received
10 – Xon received
11 – both received
00 – none
01 – Xon transmitted
10 – Xoff transmitted
11 – Illegal, does not occur
00 – normal
01 – TxD halt pending
10 – re–enabled
11 – flow disabled
00 – normal TxD data
01 – wait on normal data
10 – Xoff in pending
11 – Xon in pending
XISR[7:6] – Received X Character Status. This field can be read to
determine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
XISR[5:4] – Automatic transmission Status. This field indicates the
last flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b’10, it is the
user’s responsibility to transmit an Xon, when appropriate.
XISR[3:2] – TxD flow Status. This field tracks the transmitter’s flow
status as follows:
00 – normal. The flow control is under host control.
01 – TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’00.
10 – re–enabled. The transmitter had been halted and restarted.
It is sending data characters. After a read of the XISR, it will
return to ”normal” status.
11 – disabled. The transmitter is flow controlled.
XISR[1:0] – TxD character Status. This field allows determination of
the type of character being transmitted. If XISR(1:0) is b’01, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
Table 23. WDTRCR – Watch-dog Timer Enable
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDT
h
WDT
g
WDT
f
WDT
e
WDT
d
WDT
c
WDT
b
WDT
a
1 on
0 off
1 on
0 off
1 on
0 off
1 on
0 off
1 on
0 off
1 on
0 off
1 on
0 off
1 on
0 off
This register enables the watch-dog Timer for each of the 8
receivers on the Octal UART.
Table 24. BRGTRU
– BRG Timer Reload
Registers, Upper
Bits 7:0
8 MSB of the BRG Timer divisor.
This is the upper byte of the 16 bit value used by the BRG timer in
generating a baud rate clock
Table 25. BRGTRL
– BRG Timer Reload
Registers, Lower
Bits 7:0
8 LSB of the BRG Timer divisor.
This is the lower byte of the 16 bit value used by the BRG timer in
generating a baud rate clock.
Table 26. BRGTCR – BRG Timer Control Register (BRGTCR)
Bit 7
Bit 6:4
Bit 3
Bit 2:0
BRGTCR b, Register control
BRGTCR b, Clock selection
BRGTCR a, Register control
BRGTCR a, Clock selection
0 – Resets the timer register and
holds it stopped
1 – Allows the timer register to
run.
000 – Sclk / 16
001 – Sclk / 32
010 – Sclk/ 64
011 – Sclk / 128
100 – X1
101 – X1 / 2
110 – I/O1b
111 – GIN(1)
0 – Resets the timer register and
holds it stopped.
1 – Allows the timer register to
run.
000 – Sclk / 16
001 – Sclk / 32
010 – Sclk / 64
011 – Sclk / 128
100 – X1
101 – X1 / 2
110 – I/O1a
111 – GIN(0)
Start/Stop control and clock select register for the two BRG
counters. The clock selection is for the input to the counters. It is
that clock divided by the number represented by the BRGTU and
BRGTL the will be used as the 16x clock for the receivers and
transmitters. When the BRG timer Clock is selected for the
receiver(s) or transmitter(s) the receivers and transmitters will
consider it as a 16x clock and further device it by 16. In other words
the receivers and transmitters will always be in the 16x ode of
operation when the internal BRG timer is selected for their clock.
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