參數(shù)資料
型號(hào)： 935262730528
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 4 CHANNEL(S), 500K bps, SERIAL COMM CONTROLLER, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁(yè)數(shù)： 32/52頁(yè)
文件大小： 303K
代理商： 935262730528
Philips Semiconductors
Product specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
2001 Feb 13
38
AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3V)
VCC = 3.3V ± 10%, –40 to +85°C
SYMBOL
FIG #
PARAMETER
LIMITS
UNIT
SYMBOL
FIG. #
PARAMETER
MIN.
TYP.
MAX.
UNIT
Reset Timing
tRES1
RESET pulse width
10
Sclk
Bus Timing
tAS
A0–A7 setup time before Sclk C3 rising edge
22
3
ns
tAH
A0–A7 hold time after Sclk C3 rising edge
30
12
ns
tCS
CEN setup time before Sclk C1 high (Async)
8
3
ns
tCS
CEN setup time before Sclk C2 high (Sync)
8
3
ns
tC
CEN hold time after Sclk C3 high (Sync)
25
11/2Sclk
ns
tCH
CEN hold time after Sclk C4 high (Async)
50
11/2Sclk
ns
tSTP
CEN high before next C2 to stop next cycle (Sync Mode)2
30
ns
tRWS
W–Rn setup time before Sclk C2 rising edge
7
ns
tRWH
W–Rn hold time after Sclk C3 rising edge
25
11/2Sclk
ns
tDD
Read cycle Data valid after Sclk C3 falling edge
20
40
ns
t
Read cycle data bus floating after CEN high (Async)
17
30
ns
tDF
Read cycle data bus floating after C4 end (Sync)
11
20
ns
tDS
Write cycle data setup time before Sclk C4 rising edge
25
14
ns
tDH
Write cycle data hold time after Sclk C4 rising edge
25
14
ns
tRWD
High time between CEN low (Async)
15
1/2Sclk
ns
I/O Port Pin Timing
tPS
I/O input setup time before Sclk C3 falling edge (Read IPR)
18
4
ns
tPH
I/O input hold time after Sclk C4 rising edge
12
4
ns
tPD
I/O output valid from:
tPD
Write Sclk C4 rising edge (write to IOPIOR)
50
80
ns
Interrupt Timing
IRQN from:
tIR
Internal interrupt source active bid
22
26
43
Sclk
tIR
Reset to IRQN inactive
60
90
ns
Write IMR (set or clear IMR bit)3
40
60
ns
tDD
Interrupt vector valid after C3 rising edge
20
30
ns
Tx/Rx Clock Timing
tRX
RxC high or low time
25
8
ns
f
4
RxC frequency
(16 X)
0
8
MHz
fRX4
RxC frequency
(1 X)
0
1
MHz
tTX
TxC high or low time
20
7
ns
f
4
TxC frequency
(16 X)
0
8
MHz
fTX4
TxC frequency
(1 X)
0
1
MHz
Transmitter Timing
tTXD
TxD output delay from TxC low
50
90
ns
tTCS
TxC output delay from TxD output data
–15
4
15
ns
Receiver Timing
tRXS
RxD data setup time to RxC high (data)
25
14
ns
tRXH
RxD data hold time from RxC high (data)
25
14
ns
tsSTRT
RxD data low time for receiving a valid Start Bit
17/32
bit time
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