參數(shù)資料
型號： 935262385557
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 30 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 X 1.40 MM, PLASTIC, LQFP-80
文件頁數(shù)： 33/55頁
文件大?。?/td> 318K
代理商： 935262385557
Philips Semiconductors
Preliminary specification
XA-S3
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
2000 Mar 09
39
AC ELECTRICAL CHARACTERISTICS (5 V RANGE) (continued)
This set of parameters is referenced to the XA-S3 clock output.
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
MIN
MAX
UNIT
Address Cycle
tCHLH
26
CLKOUT rising edge to ALE rising edge
–
13
ns
tCLLL
26
CLKOUT falling edge to ALE falling edge
–
9
ns
tCHAV
26
CLKOUT rising edge to address valid
–
18
ns
tCHAX
26
CLKOUT rising edge to address changing (hold time)
2
–
ns
Code Read Cycle
tCHPL
26
CLKOUT rising edge to PSEN asserted
–
14
ns
tCHPH
26
CLKOUT rising edge to PSEN de-asserted
–
12
ns
tIVCH
26
Instruction valid to CLKOUT rising edge (setup time)
20
–
ns
tCHIX
26
CLKOUT rising edge to instruction changing (hold time)
0
–
ns
tCHIZ
26
CLKOUT rising edge to Bus 3-State (code read)
–
tC–8
ns
Data Read Cycle
tCHRL
28
CLKOUT rising edge to RD asserted
–
12
ns
tCHRH
28
CLKOUT rising edge to RD de-asserted
–
10
ns
tDVCH
28
Data valid to CLKOUT rising edge (setup time)
20
–
ns
tCHDX
28
CLKOUT rising edge to Data changing (hold time)
0
–
ns
tCHDZ
28
CLKOUT rising edge to Bus 3-State (data read)
–
tC–8
ns
Data Write Cycle
tCHWL
30
CLKOUT falling edge to WR asserted
–
12
ns
tCHWH
30
CLKOUT rising edge to WR de-asserted
–
10
ns
tQVCH
30
Data valid to CLKOUT rising edge (setup time)
4
–
ns
tCHQX
30
CLKOUT rising edge to Data changing (hold time)
0
–
ns
Wait Input
tCHWTH
31
WAIT valid prior to CLKOUT rising edge8
21
4
ns
NOTES ON PAGE 41.
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