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參數(shù)資料
| 型號： | 935262383518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 30 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 9/55頁 |
| 文件大?。?/td> | 318K |
| 代理商： | 935262383518 |
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Philips Semiconductors
Preliminary specification
XA-S3
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
2000 Mar 09
17
A/D Accuracy
The XA-S3 A/D in 10 -bit mode is specified with 16 samples
averaged in order to factor out on-chip noise. In an application
where averaging 16 samples is not practical, the accuracy
specifications may be de-rated according to the number of samples
that are actually taken. The graph in Figure 5 shows the relationship
of additional A/D error to the number of samples that are averaged.
For example, if a single A/D reading is used with no averaging, the
A/D accuracy should be de-rated by
±1.25 LSB.
SU01227
1.50
1.25
1.00
0.75
0.50
0.25
0.00
12
34
56
78
910
11
12
13
14
15
16
Number of Samples
Additional
Error
(LSB)
Figure 5. A/D accuracy by number of averaging samples
(Pertains to 10-bit mode only. Note that 10-bit mode is only specified up to fC = 20 MHz.)
CR0
LSB
MSB
BIT
SYMBOL
FUNCTION
I2CON.7
CR2
I2C Rate Control, with CR1 and CR0. See text and table.
I2CON.6
ENA
Enable I2C port. When ENA = 1, the I2C port is enabled.
I2CON.5
STA
Start flag. Setting STA to 1 causes the I2C interface to attempt to gain mastership of the bus by
generating a Start condition.
I2CON.4
STO
Stop flag. Setting STO to 1 causes the I2C interface to attempt to generate a Stop condition.
I2CON.3
SI
Serial Interrupt. SI is set by the I2C hardware when a new I2C state is entered, indicating that
software needs to respond. SI causes an I2C interrupt if enabled and of sufficient priority.
I2CON.2
AA
Assert Acknowledge. Setting AA to 1 causes the I2C hardware to automatically generate
acknowledge pulses for various conditions (see text).
I2CON.1
CR1
I2C Rate Control, with CR2 and CR0. See text and table.
I2CON.0
CR0
I2C Rate Control, with CR2 and CR1. See text and table.
CR1
AA
SI
STO
STA
ENA
CR2
I2CON
Address:42Ch
Bit Addressable
Reset Value: 00h
SU00941
Figure 6. I2C Control Register (I2CON)
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