參數(shù)資料
型號(hào)： 935262383518
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 16-BIT, 30 MHz, MICROCONTROLLER, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 32/55頁(yè)
文件大?。?/td> 318K
代理商： 935262383518
Philips Semiconductors
Preliminary specification
XA-S3
XA 16-bit microcontroller
32K/1K OTP/ROM/ROMless, 8-channel 8-bit A/D, low voltage (2.7 V–5.5 V),
I2C, 2 UARTs, 16 MB address range
2000 Mar 09
38
AC ELECTRICAL CHARACTERISTICS (5 V)
VDD = 4.5 V to 5.5 V; Tamb = 0 to +70°C for commercial, Tamb = –40°C to +85°C for industrial.
SYMBOL
FIGURE
PARAMETER
LIMITS
UNIT
SYMBOL
FIGURE
PARAMETER
MIN
MAX
UNIT
External Clock
fC
32
Oscillator frequency
0
30
MHz
tC
32
Clock period and CPU timing cycle
1/fC
ns
tCHCX
32
Clock high-time (Note 7)
tC * 0.5
ns
tCLCX
32
Clock low time (Note 7)
tC * 0.4
ns
tCLCH
32
Clock rise time (Note 7)
5
ns
tCHCL
32
Clock fall time (Note 7)
5
ns
Address Cycle
tLHLL
26, 28, 30
ALE pulse width (programmable)
(V1 * tC) – 6
ns
tAVLL
26, 28, 30
Address valid to ALE de-asserted (set-up)
(V1 * tC) – 12
ns
tLLAX
26, 28, 30
Address hold after ALE de-asserted
(tC/2) – 10
ns
Code Read Cycle
tPLPH
26
PSEN pulse width
(V2 * tC) – 10
ns
tLLPL
26
ALE de-asserted to PSEN asserted
(tC/2) – 7
ns
tAVIVA
26
Address valid to instruction valid, ALE cycle (access time)
(V3 * tC) – 36
ns
tAVIVB
27
Address valid to instruction valid, non-ALE cycle (access time)
(V4 * tC) – 29
ns
tPLIV
26
PSEN asserted to instruction valid (enable time)
(V2 * tC) – 29
ns
tPHIX
26
Instruction hold after PSEN de-asserted
0
ns
tPHIZ
26
Bus 3-State after PSEN de-asserted
tC – 8
ns
tIXUA
26
Hold time of unlatched part of address after instruction latched
0
ns
Data Read Cycle
tRLRH
28
RD pulse width
(V7 * tC) – 10
ns
tLLRL
28
ALE de-asserted to RD asserted
(tC/2) – 7
ns
tAVDVA
28
Address valid to data input valid, ALE cycle (access time)
(V6 * tC) – 36
ns
tAVDVB
29
Address valid to data input valid, non-ALE cycle (access time)
(V5 * tC) – 29
ns
tRLDV
28
RD low to valid data in (enable time)
(V7 * tC) – 29
ns
tRHDX
28
Data hold time after RD de–asserted
0
ns
tRHDZ
28
Bus 3-State after RD de-asserted (disable time)
tC – 8
ns
tDXUA
28
Hold time of unlatched part of address after data latched
0
ns
Data Write Cycle
tWLWH
30
WR pulse width
(V8 * tC) – 10
ns
tLLWL
30
ALE falling edge to WR asserted
(V12 * tC) – 10
ns
tQVWX
30
Data valid before WR asserted (data set-up time)
(V13 * tC) – 22
ns
tWHQX
30
Data hold time after WR de-asserted (Note 6)
(V11 * tC) – 5
ns
tAVWL
30
Address valid to WR asserted (address set-up time) (Note 5)
(V9 * tC) – 22
ns
tUAWH
30
Hold time of unlatched part of address after WR is de-asserted
(V11 * tC) – 7
ns
Wait Input
tWTH
31
WAIT stable after bus strobe (RD, WR, or PSEN) asserted
(V10 * tC) – 30
ns
tWTL
31
WAIT hold after bus strobe (RD, WR, or PSEN) asserted
(V10 * tC) – 5
ns
NOTES ON PAGE 41.
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