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參數(shù)資料
| 型號： | 935262358026 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, UUC36 |
| 封裝： | DIE-36 |
| 文件頁數(shù)： | 8/30頁 |
| 文件大?。?/td> | 179K |
| 代理商： | 935262358026 |
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2000 Sep 29
16
Philips Semiconductors
Product specication
SDH/SONET STM16/OC48 main ampliers
OQ2538HP; OQ2538U
Notes
1. No special cooling is required in the application if the total thermal resistance Rth(j-a) is less than 90 K/W.
2. The temperature of the PCB in the vicinity of the IC is taken to be the ambient temperature.
3. The input signal must be AC-coupled to the inputs through a coupling capacitance >22 nF.
4. Vi(p-p) is the input signal on IN and INQ for full output clipping. It is assumed that both inputs carry a complementary
signal of the specified peak-to-peak value. The lower specified limit is usually called the input sensitivity. This value
is defined as a 20% increase in rise and fall times when compared to rise and fall times with a complementary input
signal of 10 mV (p-p) applied to IN and INQ.
5. The DC voltage is fixed internally; only AC-coupling of the input signal is allowed.
6. VIO = V IN V INQ
7. See Section “RF input matching circuit” for detailed information.
8. All signal ports are AC-matched to 50
and are measured at 1 GHz (see Fig.7). Flatness deviations are within ±3dB
over the entire bandwidth.
9. See Section “RF gain and group delay measurements”.
10. F is the noise figure for a differential application and is measured at 1 GHz. See Section “Noise figure
measurements”.
11. An external 100 nF capacitor is connected at each output to remove any spurious high frequency signals.
Any circuitry driven from these pins must have an input impedance >50 k
.
12. Voltage difference between AGC (LOS) and AGCDC (LOSDC), measured with a differential square wave input
signal of 600 mV (p-p) on IN and INQ.
13. The offset is measured with inputs IN and INQ shorted together.
14. The band gap voltage may not be used as an external reference.
15. Both outputs are connected to ground through a 50
load resistance and carry complementary signals.
16. The output levels are dependent on load impedance. The specified values assume an external load impedance of
50
. If the external 100 matching resistors are connected at pins OUT and OUTQ, the output levels will fall to
75% of the specified values (see also Section “RF gain and group delay measurements”).
Band gap reference decoupling: CAPA
VO
decoupling voltage
referenced to VEE;
open output
2.9
V
Main amplier outputs: OUT and OUTQ; note 15
VOH
HIGH-level output voltage
20
50
mV
VOL
LOW-level output voltage
note 16
280
200
140
mV
tr
differential output rise time
input signal >2.5 mV (p-p)
100
150
ps
tf
differential output fall time
input signal >2.5 mV (p-p)
100
150
ps
Zo
single-ended output impedance
see Fig.6
83
100
117
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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