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參數(shù)資料
| 型號： | 935261615112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO28 |
| 封裝： | 7.50 MM, PLASTIC, SO-28 |
| 文件頁數(shù)： | 26/48頁 |
| 文件大?。?/td> | 356K |
| 代理商： | 935261615112 |
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1998 Oct 06
32
Philips Semiconductors
Preliminary specication
Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)
UDA1321
SDA and SCL lines (standard I2C-bus); see Fig.7
fSCL
SCL clock frequency
0
100
kHz
tBUF
bus free time between a STOP
and START condition
4.7
s
tHD;STA
hold time (repeated) START
condition
4.0
s
tLOW
SCL LOW time
4.7
s
tHIGH
SCL HIGH time
4.0
s
tSU;STA
set-up time for a repeated START
condition
4.7
s
tSU;STO
set-up time for a STOP condition
4.0
s
tHD;DAT
data hold time
5.0
0.9
s
tSU;DAT
data set-up time
250
ns
tr
rise time of both SDA and SCL
signals
1000
ns
tf
fall time of both SDA and SCL
signals
300
ns
CL(bus)
load capacitance for each bus line
400
pF
Oscillator; note 1
fosc
oscillator frequency
48
MHz
δ
duty factor
50
%
gm
transconductance
13.5
23.0
30.5
mS
Ro
output resistance
450
700
1450
Ci(XTAL1)
parasitic input capacitance at XTAL1
10
11
12
pF
Ci(XTAL2)
parasitic input capacitance at XTAL2
4.5
5.0
5.5
pF
Istart
start current
4.3
8.8
15.0
mA
Power-on reset
tsu(POR)
power-on reset set-up time
notes 2 and 3
5Cref
ms
Filter Stream DAC (FSDAC)
RES
resolution
16
bits
Vo(FS)(rms)
full-scale output voltage
(RMS value)
VDD = 3.3 V
0.66
V
SVRR
supply voltage ripple rejection of
VDDA and VDDO
fripple = 1 kHz;
Vripple(p-p) = 0.1 V
60
dB
V
o
channel unbalance
maximum volume
0.03
dB
α
ct
crosstalk between channels
RL =5k
95
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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