參數(shù)資料
型號: 935261504551
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: PLASTIC, SOT-307, QFP-44
文件頁數(shù): 52/87頁
文件大小: 440K
代理商: 935261504551
1999 Jul 01
56
Philips Semiconductors
Product specication
9-bit video input processor
SAA7113H
15.2.9
SUBADDRESS 08H
Table 35 Sync control SA 08, D7 to D5, D3 to D0
FUNCTION
CONTROL BIT
LOGIC LEVEL
DATA BIT
Vertical noise reduction (VNOI)
Normal mode (recommended setting)
VNOI1
0
D1
VNOI0
0
D0
Fast mode [applicable for stable sources only;
automatic eld detection (AUFD) must be disabled]
VNOI1
0
D1
VNOI0
1
D0
Free running mode
VNOI1
1
D1
VNOI0
0
D0
Vertical noise reduction bypassed
VNOI1
1
D1
VNOI0
1
D0
Horizontal PLL (HPLL)
PLL closed
HPLL
0
D2
PLL open; horizontal frequency xed
HPLL
1
D2
Horizontal time constant selection (HTC1 and HTC0)
TV mode (recommended for poor quality TV signals
only; do not use for new applications)
HTC1 and HTC0
00
D4 and D3
VTR mode (recommended if a deection control circuit
is directly connected to SAA7113H)
HTC1 and HTC0
01
D4 and D3
Reserved
HTC1 and HTC0
10
D4 and D3
Fast locking mode (recommended setting)
HTC1 and HTC0
11
D4 and D3
Forced ODD/EVEN toggle FOET
ODD/EVEN signal toggles only with interlaced source
FOET
0
D5
ODD/EVEN signal toggles eldwise even if source is
non-interlaced
FOET
1
D5
Field selection (FSEL)
50 Hz, 625 lines
FSEL
0
D6
60 Hz, 525 lines
FSEL
1
D6
Automatic eld detection (AUFD)
Field state directly controlled via FSEL
AUFD
0
D7
Automatic eld detection
AUFD
1
D7
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