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| 型號(hào)： | 935242220551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 75/148頁(yè) |
| 文件大?。?/td> | 692K |
| 代理商： | 935242220551 |
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1998 Apr 09
32
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.2.6
STATUS INFORMATION OF THE PCI INTERFACE
Table 9 lists the status information that the PCI interface makes available to the user in addition to the interrupt sources
that are described later. This information is read only.
Table 9
Status bits of the DMA control
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
120
VDP1
31 to 0
R
logical video DMA pointer of FIFO 1
124
VDP2
31 to 0
R
logical video DMA pointer of FIFO 2l
128
VDP3
31 to 0
R
logical video DMA pointer of FIFO 3
12C
ADP1
31 to 0
R
logical audio DMA pointer of audio output FIFO A1_out
130
ADP2
31 to 0
R
logical audio DMA pointer of audio input FIFO A1_in
134
ADP3
31 to 0
R
logical audio DMA pointer of audio output FIFO A2_out
138
ADP4
31 to 0
R
logical audio DMA pointer of audio input FIFO A2_in
13C
DDP
31 to 0
R
logical DEBI DMA pointer
7.3
Main control
7.3.1
GENERAL
The SAA7146A has two Dwords of general control to
support quick enable/disable switching of any activity of
the SAA7146A via direct access by the CPU. These main
control Dwords are split in two parts. The upper parts have
16 bits of bit-mask to allow bit-selective write to the lower
part which contains single bit enable/disable control of
major interface functions of SAA7146A. If a certain bit
position is masked with a logic 1 in the mask word (upper
2 bytes) during a write access, then the corresponding bit
in the control word (lower 2 bytes) is changed according to
the contents of the transmitted data. By that the CPU can
easily switch on or off certain selected interfaces of the
SAA7146A without checking the actual ‘remaining’
programming (enabling) of the other parts.
The programming of registers for the 3 Video DMA
channels, both video processors (HPS, BRS) and for the
interfaces DEBI and I2C-bus is performed by an upload
method. This is done to guarantee coherent programming
data. During initiation of an upload operation from a
shadow RAM each of the UPLD bits [10 to 0] (see
Table 11) is assigned to a set of registers. If a logic 1 is
written into a UPLD bit all dedicated shadow RAM
registers containing changed data are uploaded into their
working registers immediately. During a read cycle the
UPLD bits give information on whether the shadow RAM
contains changed data not yet uploaded into the working
registers. The UPLD bits remain HIGH as long as the
contents of the shadow RAM represents the current
programming
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