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參數(shù)資料
| 型號(hào)： | 935242220551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 128/148頁(yè) |
| 文件大?。?/td> | 692K |
| 代理商： | 935242220551 |
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1998 Apr 09
80
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Fig.27 Sync and data path for direct and line memory mode.
handbook, full pagewidth
MGG268
DMA
READ
DATA
FIFO empty
PXQ
(write enable in line
memory mode)
PXQ
FIFO3
Dword request
PCI
BRS
DATA
VS
HS
LLC
D1 INTERFACE
7.10.3
VBI DATA INTERFACE
The SAA7146A transports VBI data (data during the
Vertical Blanking Interval) or VBI test signals between real
time world and the computer system. The data can be in
YUV format, luminance Y only, encoded digital CVBS on
luminance channel or a single bit stream of sliced data.
1 or 2 MSB of Y is utilized to carry ‘data bit’. PXQ pixel
qualifier is used as ‘data clock’.
7.11
Video data formats on the PCI-bus
The big/little-endian is supported in the way that a 2 and a
4-byte swapping is possible. The data formats using
32 bits per pixel requires a 4-byte swap, whereas the data
formats using 16 bits per pixel requires a 2-byte swap.
7.11.1
SCALER OUTPUT FORMATS (HPS)
7.11.1.1
RGB
RGB each defined as ‘full range’, all bits = 0 for black and
all bits = 1 for white. All RGB formats are composed
formats and use video FIFO 1 and video DMA Channel 1.
αRGB-32: the αRGB format use a full byte for each
colour component and one byte for the colour key
information. The bytes are packed cyclicly into Dwords
and uses one Dword per sample. ‘
α’ can be the colour
key bit in all 8 bits or read via FIFO 2 (see
Section 7.11.1.3) and uses one entire Dword per
sample (see Table 59).
RGB-24 packed: The 24-bit RGB format use a full byte
for each colour component. The bytes are packed
cyclicly into Dwords, uses 0.75 Dwords per sample, i.e.
3 Dwords per 4 samples. The byte phase of the first
sample on each line is defined by the 2 LSBs of the DMA
base (see Table 60).
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