- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36334 > 935242210551 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935242210551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 6/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935242210551 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)當(dāng)前第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)
1998 Apr 09
103
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.15.4.1
Target bus cycle in Intel mode
The SAA7146A starts a target transfer cycle by placing the
target address on the multiplexed address/data lines
(AD15 to AD0). The Address Latch Enable (ALE) is then
asserted (set LOW) indicating that the address lines
AD15 to AD0 and the SBHE signal are valid (the active
LOW SBHE indicates data transfer on the high byte lane
AD15 to AD8). After asserting ALE the AD lines are
multiplexed for data transfer. Valid data on the AD lines is
indicated by assertion of WRN in the write mode (data from
SAA7146A to target), or by assertion of RDN in the read
mode (data from target to SAA7146A). In the read mode,
it is the responsibility of the target to place data on the AD
lines as soon as possible following the assertion of RDN.
If the target does not require wait states or handshake for
data transfer, RDY should then be tied HIGH and the
TIMEOUT value should be set to 0. If the target requires
wait states, but still does not utilize handshake, then the
TIMEOUT value can be increased. The width of both WRN
and RDN pulses will be increased by 1 PCI cycle for each
count in the TIMEOUT value. If the target is capable of
handshake, to indicate when it is ready for data transfer,
then the RDY signal can be used.
Since the SAA7146A will not evaluate the RDY signal until
TIMEOUT + 1 PCI cycles have elapsed, it is
recommended that TIMEOUT be set to a minimum value
(usually 0) for maximum throughput. If the target is slow in
responding to the RDN/WRN then TIMEOUT can be
increase to allow the target time to de-assert RDY (pull to
LOW level) for the current data cycle. Once the
TIMEOUT + 1 number of PCI cycles have elapsed (from
the assertion of RDN/WRN) the transfer control is in a ‘wait
for RDY high’ state. The data transfer cycle will be ended
when a TIMEOUT condition at RDY HIGH or a rising edge
of RDY after TIMEOUT is detected. The cycle is ended by
de-asserting ALE, SBHE and RDN/WRN.
It should be noted that in the INTEL mode the timer must
be enabled (TIEN = 0). The TIMEOUT counter is used as
‘delay sampling RDY’ value to accommodate target
reaction delay in generating a valid RDY signal. TIMEOUT
is NOT used as an overall cycle watchdog timer (i.e.: to
terminate the cycle if RDY fails to become de-asserted).
The current cycle will not end and a new cycle will not start
until RDY is asserted (HIGH).
Fig.31 Intel style transfer.
handbook, full pagewidth
MHB063
address phase
tdsw
taz
tmin
address
write data
read data
data phase
tah
tas
tdhr
tdsrd
tdsrh
tdz
tidl
tdhw
talh
trdy
AD(WR)
AD(RD)
SBHE
ALE
RDN
WRN
RDY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935242210557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935262922551 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935262922557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935242220551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935242220557 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935245650125 | 制造商:NXP Semiconductors 功能描述:Inverter 1-Element CMOS 5-Pin TSSOP T/R |
| 935248-90 | 制造商:JANCO 功能描述:935248-90 |
| 9-3525-012 | 制造商:KEYSTONE 功能描述:MODIFIED 3525,VERSION E |
| 935252-5 | 制造商:C-H 功能描述:935252-5 |
| 935257650112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY ICSUBS TO 935257650112 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。