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| 型號(hào)： | 935225400512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 18/67頁 |
| 文件大小： | 400K |
| 代理商： | 935225400512 |
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1998 Apr 07
25
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
11 I/O FACILITIES
The P89C738 has 4 and P89C739 has 6 8-bit ports.
Ports 0 to 3 are the same as in the 80C51, with the
exception of the additional function of Port 1. Port lines
P1.0 and P1.1 may be used as inputs for Timer 2, P1.1
may also be used as an additional (third) external interrupt
request input.
Ports 0, 1, 2, and 3 perform the following alternative
functions:
Port 0 Provides the multiplexed low-order address and
data bus used for expanding the P89C738 with
standard memories and peripherals.
Port 1 Pins can be configured individually to provide:
external interrupt request input (external
interrupt 2); external inputs for Timer/counter 2.
Port 2 Provides the high-order address bus when
expanding the P89C738 with external program
memory and/or external data memory.
Port 3 Pins can be configured individually to provide:
external interrupt request inputs (external
interrupt 0/1); external inputs for Timer/counter 0
and Timer/counter 1; Serial Port receiver input and
transmitter output control signals to read and write
external data memory.
Bits which are not used for the alternative functions may be
used as normal bidirectional I/O pins. The generation or
use of a Port 1 or Port 3 pin as an alternative function is
carried out automatically by the P89C738 provided the
associated SFR bit is HIGH. Otherwise the port pin is held
at a logical LOW level.
Fig.15 I/O buffers in the P89C738; P89C739 (Ports 1, 2, 3, 4 and 5).
handbook, full pagewidth
MGG025
p1
p2
p3
input data
read port pin
2 oscillator
periods
n
strong pull-up
I/O PIN
VDD
I1
Q
from port latch
INPUT
BUFFER
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