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參數(shù)資料
| 型號(hào)： | 935225400512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁(yè)數(shù)： | 17/67頁(yè) |
| 文件大小： | 400K |
| 代理商： | 935225400512 |
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1998 Apr 07
24
Philips Semiconductors
Product specication
8-bit Flash microcontrollers
P89C738; P89C739
10.3
Watchdog Timer (T3)
The Watchdog Timer (see Fig.14), consists of an 11-bit
prescaler and an 8-bit timer formed by SFR T3. The timer
is incremented every 1.5 ms, which is derived from the
system clock frequency of 16 MHz by the following
formula:
The 8-bit timer increments every 12
× 2048 cycles of the
on-chip oscillator. When a timer overflow occurs, the
microcontroller is reset. The internal reset signal is not
inhibited when the external RST pin is kept LOW, e.g. by
an external reset circuit. The reset signal drives Ports 1, 2,
3, 4 and 5 outputs into the HIGH state and Port 0 into
high-impedance, no matter whether the clock oscillator is
running or not.
To prevent a system reset the timer must be reloaded in
time by the application software. If the processor suffers a
hardware/software malfunction, the software will fail to
reload the timer. This failure will result in a reset upon
overflow thus preventing the processor running out of
control.
f
timer
f
clk
12
2048
×
()
---------------------------------
=
This time interval is determined by the 8-bit reload value
that is written into register T3:
The Watchdog Timer can only be reloaded if the condition
flag WLE (PCON.4) has been previously set HIGH by
software. At the moment the counter is loaded WLE is
automatically cleared.
In the Idle mode the Watchdog Timer and reset circuitry
remain active.
The Watchdog Timer is controlled by the Watchdog enable
signal EW (EBTCON.1). A HIGH level enables the
Watchdog Timer and disables the Power-down mode.
A LOW level disables the Watchdog Timer and enables
the Power-down mode.
Watchdog time interval
T3
[] 12
×
2048
×
f
clk
----------------------------------------------
=
Fig.14 Watchdog Timer block diagram.
handbook, full pagewidth
MBH081
INTERNAL BUS
1/12 fclk
write
T3
PRESCALER
11-BIT
TIMER T3 (8-BIT)
LOAD
CLEAR
to reset circuitry
LOADEN
EW
LOADEN
PCON.4
PCON.1
CLEAR
WLE
PD
INTERNAL BUS
(1)
(1) See Fig.21.
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