參數(shù)資料
型號(hào)： 935210150512
廠商： NXP SEMICONDUCTORS
元件分類： 光電元器件
英文描述： 1 CHANNEL READ WRITE AMPLIFIER CIRCUIT, PDSO24
封裝： 7.50 MM, PLASTIC, SOT-137-1, SOP-24
文件頁(yè)數(shù)： 25/26頁(yè)
文件大?。?/td> 203K
代理商： 935210150512
1998 Mar 17
8
Philips Semiconductors
Preliminary specication
QIC read-write amplier
TZA1000
DACs
There are 3 internal DACs:
1. The Sense DAC: current DAC; 7-bit resolution
2. The Write DAC: current DAC; 7-bit resolution
3. The Bias DAC: voltage DAC; 5-bit resolution.
The Sense and Write DAC current settings are a function
of the reference current Iref (at the Iref pin). Iref is multiplied
by a 7-bit factor: S0 to S6 for the sense DAC, W0 to W6 for
the write DAC (see Tables 14 and 15). If the resistance
between Iref and GND is increased (or decreased), the
DAC output currents will be decreased (or increased) by
the same factor. In this way, the DAC output current
ranges can be adjusted.
The current values specified, and the equations used to
calculate Sense and Write currents (see Tables 14
and 15), are for a 430
resistance between Iref and GND.
This resistance can be varied between 250
and 1 k,
giving a
±2 × DAC modification range. For reasons of
noise and stability, the voltage at the Iref pin should not be
used in any other part of the circuit.
Clock handling
The TZA1000 has 2 clock inputs:
CLK: the general clock input, pin 15
SCLK: the serial interface clock input, pin 10.
CLK is used for status register read and write cycle timing
and for operating the internal AGC. When the AGC is not
being used and serial communications are not active, CLK
may be switched off. This can help reduce crosstalk on the
printed circuit board.
When accessing the status register, the CLK frequency
must be at least 16
× SCLK frequency. It is recommended
that the 24 MHz clock supplied by the SZA1000 be used
directly.
Serial interface
The 3 wire serial interface recognizes 8-bit addresses and
8-bit data. To read data from the status register, hex
address FF must be transmitted. The IC will then respond
with the contents of the 8-bit status register.
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