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參數(shù)資料
| 型號： | 935206130112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | OT PLD, 35 ns, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153AC, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 225K |
| 代理商： | 935206130112 |
Philips Semiconductors
Product specification
PLC18V8Z
Zero standby power
CMOS versatile PAL devices
1997 Aug 08
12
POWER-UP RESET
In order to facilitate state machine design and testing, a power-up
reset function has been incorporated in the PLC18V8Z. All internal
registers will reset to Active-Low (logical “0”) after a specified period
of time (tPPR). Therefore, any OMC that has been configured as a
registered output will always produce an Active-High on the
associated output pin because of the inverted output buffer. The
internal feedback (Q) of a registered OMC will also be set Low. The
programmed polarity of OMC will not affect the Active-High output
condition during a system power-up condition.
TIMING DIAGRAMS
Switching Waveforms
VALID INPUT
3–STATE
3-STATE
INPUTS
I/O, REG.
FEEDBACK
CLK
PIN 11 OE
REGISTERED
OUTPUTS
ANY INPUT
PROGRAMMED FOR
DIRECTION CONTROL
COMBINATORIAL
OUTPUTS
tIS
tIH
tCKH
tCKL
tCKP
tCKO
tOD1
tOD2
tOE2
tPD
tOE1
Power-Up Reset
NOTE:
Diagram presupposes that the outputs (F) are enabled. The reset occurs regardless of the output condition (enabled or disabled).
tCKP
tCKH
tCKL
tIS
1.5V
tCKL
tIH
tIS
1.5V
tCKO
1.5V
tPPR
4.5V
3.0V
+5V
0V
VOH
VOL
+3V
0V
+3V
0V
VCC
F
(OUTPUTS)
I, B
(INPUTS)
CLK
SP00020
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