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參數(shù)資料
| 型號： | 935201500512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOT-341-1, SSOP-28 |
| 文件頁數(shù)： | 29/29頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935201500512 |
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1996 Mar 21
9
Philips Semiconductors
Product specication
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
Notes
1. In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock
must not be less than 0.5 ns.
2. Analog input voltages producing code 0 up to and including code 1023:
a) VosB (voltage offset BOTTOM) is the difference between the analog input which produces data equal to 00 and
the reference voltage BOTTOM (VRB) at Tamb =25 °C.
b) VosT (voltage offset TOP) is the difference between VRT (reference voltage TOP) and the analog input which
produces data outputs equal to code 1023 at Tamb =25 °C.
3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities
of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to
pins VRB and VRT via offset resistors ROB and ROT as shown in Fig.3.
a) The current flowing into the resistor ladder is IL =
and the full-scale input range at the converter,
to cover code 0 to code 1023, is .
b) Since RL, ROB and ROT have similar behaviour with respect to process and temperature variation, the ratio
will be kept reasonably constant from part to part. Consequently variation of the output codes
at a given input voltage depends mainly on the difference VRT VRB and its variation with temperature and supply
voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching
between each of them is then optimized.
4.
DIFFERENTIAL GAIN; note 9
Gdiff
differential gain
fclk = 80 MHz;
PAL modulated ramp
0.5
%
DIFFERENTIAL PHASE; note 9
diff
differential phase
fclk = 80 MHz;
PAL modulated ramp
0.5
deg
Timing (fclk = 80 MHz; CL = 15 pF); see Fig.4; note 10
tds
sampling delay time
2ns
th
output hold time
5
ns
td
output delay time
913
ns
CL
digital output load capacitance
15
20
pF
3-state output delay times; see Fig.5
tdZH
enable HIGH
45
50
ns
tdZL
enable LOW
25
35
ns
tdHZ
disable HIGH
12
15
ns
tdLZ
disable LOW
12
15
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
RT
V
RB
–
R
OB
R
L
R
OT
++
------------------------------------------
V
I
R
L
I
L
×
R
L
R
OB
R
L
R
OT
++
------------------------------------------
V
RT
V
RB
–
()
0.824
V
RT
V
RB
–
()
×
=
×
=
R
L
R
OB
R
L
R
OT
++
-----------------------------------------
GER
V
1023
V
0
–
() 2V
–
2V
------------------------------------------------
100
×
=
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