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參數(shù)資料
| 型號(hào)： | 935201500512 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | ADC |
| 英文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOT-341-1, SSOP-28 |
| 文件頁數(shù)： | 27/29頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 935201500512 |
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1996 Mar 21
7
Philips Semiconductors
Product specication
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
Reference voltages for the resistor ladder; see Table 1
VRB
reference voltage BOTTOM
1.2
1.3
V
VRT
reference voltage TOP
3.8
VCCA 0.8 V V
Vdiff
differential reference voltage
VRT VRB
1.8
2.5
3.0
V
Iref
reference current
28
mA
RLAD
resistor ladder
90
TCRLAD
temperature coefcient of the
resistor ladder
1860
ppm
167
m
/K
VosB
offset voltage BOTTOM
note 2
220
VosT
offset voltage TOP
note 2
220
mV
VI(p-p)
analog input voltage
(peak-to-peak value)
note 3
1.5
2.06
2.5
V
Outputs
DIGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
VOL
LOW level output voltage
IO = 1 mA
0
0.4
V
VOH
HIGH level output voltage
IO = 0 mA
2.7
VCCO 0.5
V
IO = 0.4 mA
2.7
VCCO 1.3
V
IO = 1 mA
2.4
VCCO 1.4
V
IOZ
output current in 3-state mode
0.4 V < VO <VCCO
20
+20
A
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)
maximum clock frequency
TDA8762A/6
60
MHz
TDA8762A/8
80
MHz
tCPH
clock pulse width HIGH
5
ns
tCPL
clock pulse width LOW
5
ns
Analog signal processing
LINEARITY
INL
integral non-linearity
fclk = 80 MHz; ramp input
±0.75
±1.5
LSB
DNL
differential non-linearity
fclk = 80 MHz; ramp input
±0.3
±0.7
LSB
OFER
offset error
middle code; VRB = 1.3 V;
VRT = 3.8 V
±1
LSB
GER
gain error (from device to device)
VRB = 1.3 V; VRT = 3.8 V;
note 4
±0.1
%
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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