參數(shù)資料
型號(hào)： 935198960112
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQCC44
封裝： PLASTIC, SOT-187, LCC-44
文件頁(yè)數(shù)： 3/18頁(yè)
文件大?。?/td> 143K
代理商： 935198960112
1997 Jun 10
11
Philips Semiconductors
Preliminary specication
PANorama-IC (PAN-IC)
SAA4995WP
MICROCONTROLLER BUS TIMING (SNERT BUS)
MICROCONTROLLER BUS CONTROL (SNERT BUS)
The following control table applies (Table 5), for control via the microcontroller bus (SNERT bus, consisting of SNCL,
SNDA and VRST signals). Data communication is by writing to the PAN-IC (address 40H to 48H) and reading from it
(address 49H)
Table 5
SNERT-bus control
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Tcy(SNCL)
SNCL cycle time
see Fig.7
1
s
tsu(i)
input data set-up time
see Fig.7
90
ns
th(i)
input data hold time
see Fig.7
50
ns
th(o)(D)
output data hold time
see Fig.7
0
ns
td
output data delay time
see Fig.7
700
ns
ADDRESS
(HEX)
FUNCTION
# OF BITS
BIT
POSITION
REMARKS
40
X1l
8
7 : 0
denition of X1l with a resolution of 4 samples; see Fig.3 and
note 1
41
X0l
8
7 : 0
denition of X0l with a resolution of 4 samples; see Fig.3 and
note 1
42
X0r
8
7 : 0
denition of X0r with a resolution of 4 samples; see Fig.3 and
note 1
43
X1r
8
7 : 0
denition of X1r with a resolution of 4 samples; see Fig.3 and
note 1
44
output samples
per line
8
7 : 0
resolution of 4 luminance samples; actual #
samples = (programmed # samples + 1)
× 4; note 2
Fig.7 SNERT bus interface timing.
handbook, full pagewidth
MGK181
SNCL
LSB
SNDA
(receiver
mode)
SNDA
(transmitter
mode)
data
valid
data
valid
data
valid
data
valid
data
valid
tsu(i)
th(i)
th(o)(D)
td
Tcy(SNCL)
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