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參數(shù)資料
| 型號： | 933783430005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 56K |
| 代理商： | 933783430005 |
September 1993
7
Philips Semiconductors
Product specication
Octal D-type ip-op with reset;
positive-edge trigger
74HC/HCT273
AC WAVEFORMS
Fig.6
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width output
transition times and the maximum clock pulse frequency.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays
and the master reset to clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
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