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參數(shù)資料
| 型號(hào)： | 933713760653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 118K |
| 代理商： | 933713760653 |
December 1990
2
Philips Semiconductors
Product specication
Quad 2-input multiplexer; inverting
74HC/HCT158
FEATURES
Inverting data path
Output capability: standard
ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT158 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT158 are quad 2-input multiplexers which
select 4 bits of data from two sources and are controlled by
a common data select input (S). The four outputs present
the selected data in the inverted form. The enable input (E)
is active LOW.
When E is HIGH, all the outputs (1Y to 4Y) are forced
HIGH regardless of all other input conditions.
Moving the data from two groups of registers to four
common output buses is a common use of the “158”. The
state of S determines the particular register from which the
data comes. It can also be used as a function generator.
The device is useful for implementing highly irregular logic
by generating any four of the 16 different functions of two
variables with one variable common.
The ”158” is the logic implementation of a 4-pole,
2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations for the output are:
1Y = E.(1l1.S + 1l0.S)
2Y = E.(2l1.S + 2l0.S)
3Y = E.(3l1.S + 3l0.S)
4Y = E.(4l1.S + 4l0.S)
The “158” is identical to the “157” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC = 5 V
nI0, nI1 to nY
12
13
ns
E to nY14
16
ns
S to nY14
16
ns
CI
input capacitance
3.5
pF
CPD
power dissipation capacitance per multiplexer
notes 1 and 2
40
pF
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