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參數(shù)資料
| 型號： | 933713760653 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | HC/UH SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16 |
| 封裝： | SOT-109, SO-16 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 118K |
| 代理商： | 933713760653 |
Philips Semiconductors - PIP - 74HC/HCT158; Quad 2-input multiplexer; inverting
Product Information
74HC/HCT158;
Quad 2-input
multiplexer;
inverting
Information as of 2003-04-23
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Download datasheet
Applications
Block diagram
topGeneral description
The 74HC/HCT158 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT158 are quad 2-input multiplexers which select 4 bits of data from two sources and are
controlled by a common data select input (S). The four outputs present the selected data in the inverted form.
The enable input (E) is active LOW.
When E is HIGH, all the outputs (1Y to 4Y) are forced HIGH regardless of all other input conditions.
Moving the data from two groups of registers to four common output buses is a common use of the '158'. The
state of S determines the particular register from which the data comes. It can also be used as a function
generator.
The device is useful for implementing highly irregular logic by generating any four of the 16 different functions
of two variables with one variable common.
The '158' is the logic implementation of a 4-pole, 2-position switch, where the position of the switch is
determined by the logic levels applied to S.
The logic equations for the output are:
1Y = E.(1l1.S + 1l0.S)
2Y = E.(2l1.S + 2l0.S)
3Y = E.(3l1.S + 3l0.S)
4Y = E.(4l1.S + 4l0.S)
The '158' is identical to the '157' but has inverting outputs.
file:///G|/imaging/BITTING/CPL/20030424/04232003_9/PHGL/_HTML04232003/74HCT158N.html (1 of 4) [Apr-29-2003 2:46:35 PM]
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