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參數(shù)資料
| 型號(hào)： | 933646820602 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | F/FAST SERIES, OCTAL 1-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, SOT-146-1, DIP-20 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 146K |
| 代理商： | 933646820602 |
Philips Semiconductors
Product data
74F373/74F374
Latch/flip-flop
74F373 Octal transparent latch (3-State)
74F374 Octal D-type flip-flop (3-State)
2
2002 Nov 20
FEATURES
8-bit transparent latch — 74F373
8-bit positive edge triggered register — 74F374
3-State outputs glitch free during power-up and power-down
Common 3-State output register
Independent register and 3-State buffer operation
SSOP Type II Package
DESCRIPTION
The 74F373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is HIGH. The latch remains transparent to the data
input while E is HIGH, and stores the data that is present one set-up
time before the HIGH-to-LOW enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is LOW, latched or
transparent data appears at the output.
When OE is HIGH, the outputs are in high impedance “off” state,
which means they will neither drive nor load the bus.
The 74F374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
set-up time before the LOW-to-HIGH clock transition is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is LOW, the data in
the register appears at the outputs. When OE is HIGH, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
TYPE
TYPICAL
PROPAGATION
DELAY
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F373
4.5 ns
35 mA
TYPE
TYPICAL fmax
TYPICAL SUPPLY
CURRENT
(TOTAL)
74F374
165 MHz
55 mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
PKG DWG #
VCC = 5 V ±10%, Tamb = 0 °C to +70 °C
20-pin plastic DIP
N74F373N, N74F374N
SOT146-1
20-pin plastic SOL
N74F373D, N74F374D
SOT163-1
20-pin plastic SSOP type II
N74F373DB, N74F374DB
SOT339-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS
DESCRIPTION
74F (U.L.)
HIGH / LOW
LOAD VALUE
HIGH/LOW
D0 - D7
Data inputs
1.0 / 1.0
20
A / 0.6 mA
E (74F373)
Enable input (active-HIGH)
1.0 / 1.0
20
A / 0.6 mA
OE
Output enable inputs (active-LOW)
1.0 / 1.0
20
A / 0.6 mA
CP (74F374)
Clock pulse input (active rising edge)
1.0 / 1.0
20
A / 0.6 mA
Q0 - Q7
3-State outputs
150 / 40
3.0 mA / 24 mA
NOTE: One (1.0) FAST unit load is defined as: 20
A in the HIGH state and 0.6 mA in the LOW state.
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