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參數(shù)資料
| 型號： | 933637620112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 諧振器 |
| 英文描述： | 4000/14000/40000 SERIES, PRESCALER, PDIP18 |
| 封裝： | PLASTIC, SOT-102-3, DIP-18 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大小： | 115K |
| 代理商： | 933637620112 |
January 1995
8
Philips Semiconductors
Product specication
Universal timer module
HEF4753B
LSI
7. Digital pulse duration selector mode (Y = Z = LOW)
This mode is a combination of two circuits, both used for frequency recognition. Both circuits are driven by the same clock
and same input signal, but programmed for different frequencies. The LFC input of the low-frequency circuit is set to logic
LOW, the output is connected to the LFC input of the high-frequency circuit, whose output (OUT) is the ‘filter’ output. The
delay time depends on the same facts as given in note 2.. For timing diagram see Fig.9.
Notes to operating modes
1. The number of clocks for one cycle in the counter and divider mode is:
a. Contents of programmable counter plus one if X = W = LOW.
b. Contents of programmable counter multiplied by 16, 256 or 4096 if X and/or W = HIGH.
2. The delay in the modes 3, 4, 6 and 7, and the delay which is identical to the maximum duration of the transient pulse
in mode 5 depend on the optional divided clock frequency, the input conditions of the 8-bit presetable counter and in
addition, different times of propagation delays, jitter and maximum one half of a clock frequency period.
Fig.9
Timing diagram for digital pulse duration selector mode; tIN1, tIN2 and tIN3 are the IN input pulse durations;
t1 = predefined delay by programming IC1; t2 = predefined delay by programming IC2.
Minimum dividing number is 3.
A
B
C
D
E
F
G
H
W
X
LFC
Y
Z
L
HHHHH
L
H
IC1
L
HHHHHH
L
OUT
(IC1)
L
IC2
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