參數(shù)資料
型號(hào)： 932S890CKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72
封裝： ROHS COMPLIANT, MLF-72
文件頁數(shù)： 2/21頁
文件大?。?/td> 223K
代理商： 932S890CKLFT
932S890C
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
IDT
RD890 SYSTEM CLOCK FOR AMD-BASED SERVERS
10
932S890C
REV D 052011
Electrical Characteristics–USB - 48MHz, SIO 48/24MHz
Electrical Characteristics–REF-14.318MHz
PARAMETER
S YMBOL
CONDITIO NS*
MIN
TYP
MAX
UNITS
NOTES
Long Accuracy
p pm
see Tperiod min-max values
-50
+50
ppm
1,2
Clock period
TPERIOD
US B output nominal
20.702
20.833
20.964
ns
3,5
Clock Low Time
T
LOW
Measure from < 0.6V
9.375
11.458
ns
3
Clock High Time
T
HIGH
Measure from > 2.0V
9.375
11.458
ns
3
Rise Time
tr_US B
VOL = 20% of Voh,
V
OH = 80%of Voh
0.5
3
ns
1
Fall Time
t
f_USB
V
OL = 20% of Voh,
VOH = 80%of Voh
0.5
3
ns
1
Output High Voltage
VOHUSB
IOH = -1 mA
2.4
V
1,3
Output Low Voltage
VOLUSB
IOL = 1 mA
0.4
V
1,3
Output High Voltage
V
OH SIO
I
OH = -0.2 mA
1.8
2
2.2
V
1,4
Output Low Voltage
V
OLSIO
I
OL = 0.2 mA
0.4
V
1,4
Duty Cycle
d
C YCUSB
V
T = 1.5 V
45
55
%1,3
Skew
tSKEW
VT = 1.5 V
250
ps
1
Jitter, Cycle to cycle
tjCYC-CYC
VT = 1.5 V
130
ps
1,3
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2IDT recommended and/or chipset vendor layout guidelines must be followed to meet this specification
3Applies to USB outputs only
4Applies to SIO outputs only
5SIO 24MHz outputs are 1/2 of USB48MHz frequency (twice the period). Includes cycle to cycle jitter.
PARA METER
SY MBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
p pm
see Tperiod min-max values
-50
+50
ppm
1,2
Long Term Jitter
tjLT
@ 1us
50 0
ps
1,2
Clock period
T
PERIOD
14.318MHz output nominal
6 9.6378
69.8413
70.0448
ns
2,3
Clock Low Time
T
LOW
Measure from V
T = 50%
2ns
2
Clock High Time
THIGH
Measure from V T = 50%
2
ns
2
Output High Voltage
VOH
IOH = -1 mA
2.4
2.8
3.3
V
1
Output Low Voltage
VOL
IOL = 1 mA
0
0.4
V
1
Rise Time
t
R
V
OL = 20% of VOH,
VOH = 80%of VOH
1.5
ns
1
Fall Time
tF
VOL = 20% of VOH,
V
OH = 80%of VOH
1.5
ns
1
Skew
tSKEW
Measure from V T = 50%
25 0
ps
1
Duty Cycle
dt1
VT = VOH/2
45
55
%
1
Jitter, Cycle to Cycle
t
j CYC-C YC
Measure from V
T = 50%
20 0
ps
1
Jitter, P eak to Peak
tjPK-PK
Measure from V
T = 50% (0.9V)
tjpk-pk =[|tjcy c-cycmax| + |tjcyc -cycmin|]/2
20 0
ps
1
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3 Includes cycle to cycle jitter.
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