參數(shù)資料
型號: 932S825YGT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-64
文件頁數(shù): 18/20頁
文件大?。?/td> 225K
代理商: 932S825YGT
7
ICS932S825
1276F—12/02/08
Absolute Maximum Ratings
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
Conditions
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
2VDD + 0.3
V
1
Input Low Voltage
VIL
VSS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Operating Current
IDD3.3OP
all outputs driven
250
mA
Powerdown Current
IDD3.3PD
all diff pairs Low/Low
15
mA
Input Frequency
3
Fi
VDD = 3.3 V
14.318
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
5
pF
1
COUT
Output pin capacitance
6
pF
1
CINX
X1 & X2 pins
5
pF
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up or de-assertion
of PD# to 1st clock
3ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
SMBus Voltage
VDD
2.7
5.5
V
1
Low-level Output Voltage
VOL
@ IPULLUP
0.4
V
1
Current sinking at
VOL = 0.4 V
IPULLUP
4mA
1
SCLK/SDATA
Clock/Data Rise Time
3
TRI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
3
TFI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Low Current
Input Capacitance
1
Parameter
Symbol
Min
Max
Units Notes
3.3V Core Supply Voltage
VDDA
GND + 4.5V
V
1
3.3V Logic Input Supply Voltage
VDD
GND +4.5V
V
1
Storage Temperature
Ts
-50
150
°C
Ambient Operating Temp
Tambient
0
70
°C
Input ESD protection human body model
ESD prot
2000
V
1
1Operation at these extremes is neither implied nor guaranteed
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