參數(shù)資料
型號: 932S422CGLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, LEAD FREE, MO-153, TSSOP-56
文件頁數(shù): 10/21頁
文件大小: 193K
代理商: 932S422CGLF-T
18
Integrated
Circuit
Systems, Inc.
ICS932S422C
1412A—12/10/07
The time from the de-assertion of PD or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300
s of PD deassertion.
PD De-assertion
PWRDWN#
Tstable
<1.8mS
Tdrive_PwrDwn#
<300
S, >200mV
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
Test Clarification Table
Comments
FSLC/TES
T_SEL
HW PIN
FSLB/TES
T_MODE
HW PIN
TEST
ENTRY
BIT
B6b6
REF/N or
HI-Z
B6b7
OUTPUT
0X
0
X
NORMAL
10
X
0
HI-Z
10
X
1
REF/N
11
X
0
REF/N
11
X
1
REF/N
0X
1
0
HI-Z
0X
1
REF/N
B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B6b7: 1= REF/N, Default = 0 (HI-Z)
HW
SW
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V (-0.3V) then use TEST_SEL
If power-up w/ V<2.0V (-0.3V) then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input.
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B6b6.
If test mode is invoked by B6b6, only B6b7
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
相關(guān)PDF資料
PDF描述
932S422CFLF-T 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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