參數(shù)資料
型號(hào): 932S203YGLF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
封裝: 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56
文件頁(yè)數(shù): 13/18頁(yè)
文件大小: 243K
代理商: 932S203YGLF
IDTTM Frequency Generator with 133MHz Differential CPU Clocks
0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
4
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP
conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix
these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
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B#
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