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參數(shù)資料
| 型號(hào)： | 932S203AGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-56 |
| 文件頁(yè)數(shù)： | 14/19頁(yè) |
| 文件大?。?/td> | 284K |
| 代理商： | 932S203AGLF |
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4
ICS932S203
0601E—12/22/04
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull
the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the
chip is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 932S203AFLN | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203AGLFT | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203AFLNT | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203YFLFT | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203YGLF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 932S203AGLFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SERVER MAIN CLOCK RoHS:否 制造商:Silicon Labs 類(lèi)型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 932S203YFLXT | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
| 932S203YGLXT | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
| 932S208DFLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 932S208DFLFT | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 SERVER MAIN CLOCK RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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