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參數(shù)資料
| 型號： | 932S200YGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 136K |
| 代理商： | 932S200YGT |
2
ICS932S200
0427D—12/15/08
Pin Descriptions
Pin number
Pin name
Type
Description
1, 7, 8, 13, 19
20, 21, 24, 29,
38, 40, 44, 48,
52
GND
PWR
Gnd pins
3, 2
REF(1:0)
OUT
14.318MHz reference clock outputs at 3.3V
4,. 10, 16, 17,
22, 23, 27, 31,
39
VDD
PWR
Power pins 3.3V
5
X1
IN
XTAL_IN 14.318MHz crystal input
6
X2
OUT
XTAL_OUT Crystal output
9
PCICLK_F
OUT
Free running PCI clock not affected by PCI_STOP#
18, 15, 14,
12, 11
PCICLK (4:0)
OUT
PCI clock outputs at 3.3V. Synchronous to CPU clocks.
26, 25
3V66 (1:0)
OUT
66MHz outputs at 3.3V. These outputs are stopped when CPU_STOP# is
driven active..
28
SEL 133/100#
IN
This selects the frequency for the CPU and CPU/2 outputs. High =
133MHz, Low=100MHz
30
48MHz
OUT
Fixed 48MHz clock output. 3.3V
33, 32
SEL (1:0)
IN
Function select pins. See truth table for details.
34
SPREAD#
IN
Enables spread spectrum when active(Low). modulates all the CPU, PCI,
IOAPIC and 3V66 clocks. Does not affect the REF and 48MHz clocks.
0.5% down spread modulation.
35
PD#
IN
This asynchronous input powers down the chip when drive active(Low).
The internal PLLs are disabled and all the output clocks are held at a Low
state.
36
CPU_STOP#
IN
This asychronous input halts the CPUCLK and the 3V66 clocks at logic "0"
when driven active(Low).
37
PCI_STOP#
IN
This asynchronous input halts the PCICLK at logic"0" when driven
active(Low). PCICLK_F is not affected by this input.
43, 47, 51, 56
VDDL
PWR
Power pins 2.5V
50, 49, 46,
45, 42, 41
CPUCLK (5:0)
OUT
Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state
of the SEL 133/100MHz.
55, 54, 53
IOAPIC (2:0)
OUT
IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at
16.67MHz.
相關PDF資料 |
PDF描述 |
|---|---|
| 055-F24-9019A9G | 1.0/2.3 RF Connector Series |
| 932S203AFLFT | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203AGLF | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203AFLN | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 932S203AGLFT | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 932S203AFLN | 功能描述:時鐘發(fā)生器及支持產品 SERVER MAIN CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 932S203AFLNT | 功能描述:時鐘發(fā)生器及支持產品 SERVER MAIN CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 932S203AGLF | 功能描述:時鐘發(fā)生器及支持產品 SERVER MAIN CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 932S203AGLFT | 功能描述:時鐘發(fā)生器及支持產品 SERVER MAIN CLOCK RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 932S203YFLXT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Frequency Generator with 133MHz Differential CPU Clocks |
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