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參數(shù)資料
| 型號(hào)： | 9248YF-112-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 202K |
| 代理商： | 9248YF-112-T |
5
ICS9248-112
0326C—09/18/03
Byte 1: Control Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
X
#
3
S
F
6
t
i
B-
X
#
0
S
F
5
t
i
B-
X
#
2
S
F
4
t
i
B7
21
z
H
M
4
2
3
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B6
21
z
H
M
8
4
1
t
i
B-
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B0
31
F
_
M
A
R
D
S
Byte 4: Control Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
d
e
v
r
e
s
e
R
(
6
t
i
B8
1
_
6
V
3
5
t
i
B7
1
0
_
6
V
3
4
t
i
B-
X
#
C
I
P
A
O
I
_
Q
E
R
F
3
t
i
B6
41
C
I
P
A
O
I
2
t
i
B-
X
#
1
S
F
1
t
i
B3
41
1
K
L
C
U
P
C
0
t
i
B4
41
0
K
L
C
U
P
C
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B0
21
7
K
L
C
I
C
P
6
t
i
B9
11
6
K
L
C
I
C
P
5
t
i
B7
11
5
K
L
C
I
C
P
4
t
i
B6
11
4
K
L
C
I
C
P
3
t
i
B5
11
3
K
L
C
I
C
P
2
t
i
B3
11
2
K
L
C
I
C
P
1
t
i
B2
11
1
K
L
C
I
C
P
0
t
i
B1
11
0
K
L
C
I
C
P
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B1
31
7
M
A
R
D
S
6
t
i
B2
31
6
M
A
R
D
S
5
t
i
B4
31
5
M
A
R
D
S
4
t
i
B5
31
4
M
A
R
D
S
3
t
i
B6
31
3
M
A
R
D
S
2
t
i
B8
31
2
M
A
R
D
S
1
t
i
B9
31
1
M
A
R
D
S
0
t
i
B0
41
0
M
A
R
D
S
Notes:
1. Inactive means outputs are held LOW and are
disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted
logic load of the input frequency select pin conditions.
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
1
d
e
v
r
e
s
e
R
6
t
i
B-
1
d
e
v
r
e
s
e
R
5
t
i
B-
1
d
e
v
r
e
s
e
R
4
t
i
B-
1
d
e
v
r
e
s
e
R
3
t
i
B-
1
d
e
v
r
e
s
e
R
2
t
i
B-
1
d
e
v
r
e
s
e
R
1
t
i
B-
1
d
e
v
r
e
s
e
R
0
t
i
B-
1
d
e
v
r
e
s
e
R
T
I
B#
N
I
PD
W
PN
O
I
T
P
I
R
C
S
E
D
7
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register. Writing into this
register can cause malfunction
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