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參數(shù)資料
| 型號(hào)： | 9248BF-81LFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, SSOP-48 |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 568K |
| 代理商： | 9248BF-81LFT |
9
ICS9248- 81I
Advance Information
0851—08/06/03
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. SDRAM_STOP# is synchronized by the ICS9248-81I. All other clocks will continue to run while the SDRAM
clocks are disabled.The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees
the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the SDRAM clocks inside the ICS9248-81I.
3. All other clocks continue to run undisturbed.
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