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參數(shù)資料
| 型號： | 9248BF-81LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, GREEN, SSOP-48 |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 568K |
| 代理商： | 9248BF-81LF |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9248- 81I
Advance Information
0851–08/06/03
Block Diagram
Frequency Generator & Integrated Buffers
Pin Configuration
Generates the following system clocks:
- 3 CPU(2.5V/3.3V) up to 133.3MHz.
- 6 PCI(3.3V) (including 1 free-running)
- 13 SDRAMs(3.3V) up to 133.3MHz.
- 3 REF (3.3V) @ 14.318MHz
- 1 clock @ 24/14.3 MHz selectable output for SIO
- 1 Fixed clock at 48MHz (3.3V)
- 1 IOAPIC @ 2.5V / 3.3V
Skew characteristics:
- CPU – CPU<175ps
- SDRAM – SDRAM < 250ps
- CPU–SDRAM < 500ps
- CPU(early) – PCI : 1-4ns (typ. 3ns)
- PCI – PCI <500ps
Supports Spread Spectrum modulation ±0.25 &
±0.5% center spread
Serial I
2C interface for Power Management,
Frequency Select, Spread Spectrum.
Efficient Power management scheme through PCI,
SDRAM, CPU STOP CLOCKS and PD#.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
48-Pin SSOP
Power Groups
VDDREF = REF [2:0], X1, X2
VDDPCI = PCICLK_F, PCICLK [4:0]
VDDSD/C = SDRAM [11:0], supply for PLL core, 24 MHz,
48MHz
VDD/CPU = CPUCLK [3:1]
VDDLAPIC = IOAPIC
GNDFIX = Ground for fixed clock PLL and output buffers
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
The ICS9248-81I is the single chip clock solution for
Desktop/Notebook designs using the SIS style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2Cprogramming.
Spread spectrum typically reduces system EMI by 8dB to
10dB.This simplifies EMI qualification without resorting to
board design iterations or costly shielding.The ICS9248-
81I employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2C interface allows changing functions,
stop clock programming and frequency selection. The
SD_SEL latched input allows the SDRAM frequency to
follow the CPUCLK frequency(SD_SEL=1) or other clock
frequencies (SD_SEL=0)
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
I
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| 9248BF-81LFT | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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