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參數(shù)資料
| 型號(hào)： | 9148F-32 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 322K |
| 代理商： | 9148F-32 |
Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-32
Block Diagram
Pentium/ProTM System Clock Chip
9148-32 Rev B 09/09/98
Pin Configuration
48-Pin SSOP
Pentium is a trademark on Intel Corporation.
Generates system clocks for CPU, IOAPIC, PCI,
14.314 MHz REF , USB, and Super I/O
Supports single or dual processor systems
I2C interface
Supports Spread Spectrum modulation for CPU & PCI
clocks, ±0.255% Center Spread or 0 to -0.6% Down
Spread.
Skew from CPU (earlier) to PCI clock 1 to 4ns
CPU cycle to cycle jitter ±200ps
2.5V or 3.3V output: CPU, IOAPIC
3.3Voutputs: PCI, REF, 48MHz
No power supply sequence requirements
Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal
48pin300milSSOP
The ICS9148-32 is a Clock Synthesizer chip for Pentium and
PentiumPro CPU based Desktop/Notebook systems that will
provide all necessary clock timing.
Features include four CPU and eight PCI clocks. Three
reference outputs are available equal to the crystal frequency.
Additionally, the device meets the Pentium power-up
stabilization requirement, assuring that CPU and PCI clocks
are stable within 2ms after power-up.
PD# pin enables low power mode by stopping crystal OSC
and PLL stages. Other power management features include
CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#,
which stops PCICLK (0:6) clocks.
Serial I2C interface allows power management by output clock
disabling.
High drive CPUCLK outputs typically provide greater than 1
V/ns slew rate into 20pF loads. PCICLK outputs typically
provide better than 1V/ns slew rate into 30pF loads while
maintaining 50±5% duty cycle. The REF clock outputs typically
provide better than 0.5V/ns slew rates.
The ICS9148-32 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V core supply.
Power Groups
VDD = Supply for PLL core
VDD1=REF(0:2),X1,X2
VDD2=PCICLK_F,PCICLK(0:6)
VDD3=48MHz,24/48MHz#
VDDL1=IOAPIC(0:1)
VDDL2=CPUCLK(0:3)
Ground Groups
GND = Ground for PLL core
GND1=REF(0:2),X1,X2
GND2=PCICLK_F,PCICLK(0:6)
GND3=48MHz,24/48MHz#
GNDL1=IOAPIC(0:1)
GNDL2=CPUCLK(0:3)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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