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參數(shù)資料
| 型號(hào)： | 9148F-02LF |
| 廠(chǎng)商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁(yè)數(shù)： | 15/16頁(yè) |
| 文件大?。?/td> | 691K |
| 代理商： | 9148F-02LF |
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8
ICS9148-02
Power Management
ICS9148-02 Power Management Requirements
Clock Enable Configuration
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PWR PD# select pin will not cause clocks of a short or longer pulse than that of the
running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network
charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, SDRAM, PCICLK only.
The REF and IOAPIC will be stopped independant of these.
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Byte 5: Peripheral Clock Register
Notes: 1 = Enabled; 0 = Disabled, outputs held low
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Note: PWD = Power-Up Default
Byte 6: Optional Register for Future
Notes:
1. Byte 6 is reserved by Integrated Circuit Systems for
future applications.
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