參數資料
型號: 90E24PYGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO28
封裝: GREEN, SSOP-28
文件頁數: 8/54頁
文件大?。?/td> 610K
代理商: 90E24PYGI
90E21/22/23/24
SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Interface
16
March 22, 2011
4INTERFACE
4.1
SERIAL PERIPHERAL INTERFACE (SPI)
SPI is a full-duplex, synchronous channel. There are two SPI modes:
four-wire mode and three-wire mode. In four-wire mode, four pins are
used: CS, SCLK, SDI and SDO. In three-wire mode, three pins are
used: SCLK, SDI and SDO. Data on SDI is shifted into the chip on the
rising edge of SCLK while data on SDO is shifted out of the chip on the
falling edge of SCLK. The LastSPIData register (06H) stores the 16-bit
data that is just read or written.
4.1.1
FOUR-WIRE MODE
In four-wire mode, the CS pin must be driven low for the entire read
or write operation.
Read Sequence
As shown in Figure-6, a read operation is initiated by a high on SDI
followed by a 7-bit register address. A 16-bit data in this register is then
shifted out of the chip on SDO. A complete read operation contains 24
cycles.
Figure-6 Read Sequence in Four-Wire Mode
Write Sequence
As shown in Figure-7, a write operation is initiated by a low on SDI
followed by a 7-bit register address. A 16-bit data is then shifted into the
chip on SDI. A complete write operation contains 24 cycles.
Figure-7 Write Sequence in Four-Wire Mode
CS
SCLK
SDI
SDO
10
1234
5
6789
11
12
13
14
15
16
17
18
19
20
21
22
24
A0
A6
A5
A4
A3
A2
A1
Register Address
High Impedance
D15
Don't care
D0
16-bit data
23
D14 D13 D12 D11 D10 D9
D8
D7 D6
D5
D4 D3 D2
D1
CS
SCLK
SDI
SDO
10
1
2
3
4
5
6789
11
12
13
14
15
16
17
18
19
20
21
22
23
A0
A6
A5
A4
A3
A2
A1
16-bit data
High Impedance
D0
D7
D6
D5
D4
D3
D2
D1
Register Address
D15
24
D14D13 D12D11 D10 D9
D8
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