參數(shù)資料
型號(hào)： 90E24PYGI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO28
封裝： GREEN, SSOP-28
文件頁(yè)數(shù)： 2/54頁(yè)
文件大小： 610K
代理商： 90E24PYGI
90E21/22/23/24
SINGLE-PHASE HIGH-PERFORMANCE WIDE-SPAN ENERGY METERING IC
Pin Description
10
March 22, 2011
2
PIN DESCRIPTION
Table-2 Pin Description
Name
Pin No.
I/O
note 1
Type
Description
Reset
4
I
LVTTL
Reset: Reset Pin (active low)
This pin should connect to ground through a 0.1
F filter capacitor. In application it can also
directly connect to one output pin from microcontroller (MCU).
DVDD
3
I
Power
DVDD: Digital Power Supply
This pin provides power supply to the digital part. It should be decoupled with a 10
F electro-
lytic capacitor and a 0.1
F capacitor.
DGND
2
I
Power
DGND: Digital Ground
AVDD
5
I
Power
AVDD: Analog Power Supply
This pin provides power supply to the analog part. This pin should connect to DVDD through
a 10
resistor and be decoupled with a 0.1F capacitor.
Vref
13
O
Analog
Vref: Output Pin for Reference Voltage
This pin should be decoupled with a 1
F capacitor and a 1nF capacitor.
AGND
6, 14
I
Power
AGND: Analog Ground
I1P
I1N
10
11
I
Analog
I1P: Positive Input for L Line Current
I1N: Negative Input for L Line Current
These pins are differential inputs for L line current. Input range is 5
Vrms~25mVrms when
gain is '24'.
I2P
I2N
7
8
I
Analog
I2P: Positive Input for N Line Current
I2N: Negative Input for N Line Current
These pins are differential inputs for N line current. Input range is 120
Vrms~600mVrms
when gain is '1'.
Note: I2P and I2N are dedicated for the 90E23/24. They should be left open for the 90E21/
22.
VP
VN
16
15
I
Analog
VP: Positive Input for Voltage
VN: Negative Input for Voltage
These pins are differential inputs for voltage. Input range is 120
Vrms~600mVrms.
NC
9, 12
NC: This pin should be left open.
CS
24
I
LVTTL
CS: Chip Select (Active Low)
In 4-wire SPI mode, this pin must be driven from high to low for each read/write operation,
and maintain low for the entire operation. In 3-wire SPI mode, this pin must be low all the
time. Refer to section 4.1.
SCLK
25
I
LVTTL
SCLK: Serial Clock
This pin is used as the clock for the SPI interface. Data on SDI is shifted into the chip on the
rising edge of SCLK while data on SDO is shifted out of the chip on the falling edge of SCLK.
SDO
26
OZ
LVTTL
SDO: Serial Data Output
This pin is used as the data output for the SPI interface. Data on this pin is shifted out of the
chip on the falling edge of SCLK.
SDI
27
I
LVTTL
SDI: Serial Data Input
This pin is used as the data input for the SPI interface. Address and data on this pin is shifted
into the chip on the rising edge of SCLK.
MMD1
MMD0
1
28
I
LVTTL
MMD1/0: Metering Mode Configuration
00: anti-tampering mode (larger power);
01: L line mode (fixed L line);
10: L+N mode (applicable for single-phase three-wire system);
11: flexible mode (line specified by the LNSel bit (MMode, 2BH))
Note: The MMD1/0 pins are dedicated for the 90E23/24. For the 90E21/22, the metering
mode is fixed as L line mode, and MMD1 should connect to DGND and MMD0 should con-
nect to DVDD.
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