參數(shù)資料
型號: 89HPES22H16ZABR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA484
封裝: 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FCBGA-484
文件頁數(shù): 35/36頁
文件大?。?/td> 784K
代理商: 89HPES22H16ZABR
8 of 36
November 17, 2008
IDT 89HPES22H16 Data Sheet
GPIO[24]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN3
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 3
GPIO[25]1
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN4
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 4
GPIO[26]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN5
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 5
GPIO[27]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN6
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 6
GPIO[28]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN7
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 7
GPIO[29]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[30]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
GPIO[31]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: IOEXPINTN10
Alternate function pin type: Input
Alternate function: SMBus I/O expander interrupt 10
1. GPIO pins 22 and 25 are not available in the 23x23mm package.
Signal
Type
Name/Description
CCLKDS
I
Common Clock Downstream. When the CCLKDS pin is asserted, it indicates that a
common clock is being used between the downstream device and the downstream
port.
CCLKUS
I
Common Clock Upstream. When the CCLKUS pin is asserted, it indicates that a
common clock is being used between the upstream device and the upstream port.
MSMBSMODE
I
Master SMBus Slow Mode. The assertion of this pin indicates that the master SMBus
should operate at 100 KHz instead of 400 KHz. This value may not be overridden.
Table 5 System Pins (Part 1 of 2)
Signal
Type
Name/Description
Table 4 General Purpose I/O Pins (Part 4 of 4)
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