參數(shù)資料
型號: 89HPES22H16ZABR
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA484
封裝: 23 X 23 MM, 1 MM PITCH, ROHS COMPLIANT, FCBGA-484
文件頁數(shù): 23/36頁
文件大?。?/td> 784K
代理商: 89HPES22H16ZABR
3 of 36
November 17, 2008
IDT 89HPES22H16 Data Sheet
Figure 3 SMBus Interface Configuration Examples
Hot-Plug Interface
The PES22H16 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the
device, the PES22H16 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following
reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES22H16 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES22H16. In response to an I/O expander interrupt, the PES22H16 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
The PES22H16 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES22H16. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ-
ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
Signal
Type
Name/Description
PE0RP[3:0]
PE0RN[3:0]
I
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for
port 0. Port 0 is the upstream port.
PE0TP[3:0]
PE0TN[3:0]
O
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for
port 0. Port 0 is the upstream port.
PE1RP[0]
PE1RN[0]
I
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pair for
port 1.
PE1TP[0]
PE1TN[0]
O
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pair for
port 1.
PE2RP[3:0]
PE2RN[3:0]
I
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for
port 2.
PE2TP[3:0]
PE2TN[3:0]
O
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2.
Table 2 PCI Express Interface Pins (Part 1 of 3)
Processor
PES22H16
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES22H16
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
(a) Unified Configuration and Management Bus
(b) Split Configuration and Management Buses
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