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參數(shù)資料
| 型號： | 84C24 |
| 英文描述： | 84C24 Quad 10BASE-T Ethernet Media Interface Adapter manual 6/96 |
| 中文描述： | 84C24四10BASE - T以太網(wǎng)媒體接口適配器手冊6 / 96 |
| 文件頁數(shù)： | 15/51頁 |
| 文件大?。?/td> | 435K |
| 代理商： | 84C24 |
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84C24
4-15
MD400147/A
R/WSC bits are R/W bits that clear themselves after a set
period of time or after a specific event has completed. R/
LT are read bits that latch on transition, and they stay
latched until they are read. After they are read, they are
updated to their current value. R/LT bits can also be
programmed to assert the interrupt function as described
in the Interrupt section. The bit type definitions are
summarized in Table 2.
its current value. When all interrupt register bits are
cleared in all four of the Channel Status registers, the INT
pin is deasserted and the global interrupt bit INT_GLBL in
the Channel Status registers is cleared. Each interrupt bit
can be ndividually masked and subsequently be removed
as an interrupt bit by setting the appropriate mask register
bits in the Global Mask register.
As stated previously, nterrupt s asserted f one or more of
the interrupt bits has changed since the last serial read
operation. A quick way to find the bit(s) that have changed
since the last interrupt clear is to set register address bits
REGAD[3:0] = 1111. If REGAD[3:0] = 1111, the accessed
register is not determined by REGAD[3:0]. Instead, the
register accessed is the one from the Channel Status
registers where the interrupt bit has changed. After this
“interrupted” register is read out, the interrupt register bit
INT for that channel is cleared. If more than one INT
register bit s set and REGAD[3:0] = 1111 s used o access
them, the channel registers are accessed in numerical
order on each read cycle. After all INT bits have been
cleared in each Channel Status register, the INT pin is
deasserted and the INT_GLBL bits in the Channel Status
registers are cleared.
3.20.6 Register Structure
The 84C24 has ten internal 16 bit registers. A map of the
registers is shown in Table 3. The ten internal registers
consist of one Global Configuration register for setting
configurations for all four channels, four Channel Configu-
ration registers (one for each channel), four Channel
Status registers (one for each channel), and one Global
Mask register for interrupt masking of all four Channel
Status registers.
The structure and bit definition of the Global Configuration
register is shown in Table 5.
The structure and bit definitions for the Channel Configu-
ration registers is shown in Table 6. Since the channel
registers are identical in structure, the designator [m] is
used where m = 1, 2, 3, and 4 depending on which channel
register is accessed.
The structure and bit definitions for the Channel Status
register is shown in Table 7. Since the channel registers
are identical in structure, the designator [n] is used where
n = 5, 6, 7, or 8 depending on which channel register is
accessed.
The structure and bit definitions for the Global Mask
register is shown in Table 8. This register allows each R/
LT bit in the Channel Status register to be masked out or
removed as a bit that will set interrupt.
3.20.5 Interrupt
The 84C24 has a hardware and software nterrupt capabil-
ity for serial port status outputs.
As stated previously, R/LT are read bits that latch on
transition. R/LT bits are also called nterrupt bits f they are
not masked out with the Global Mask register bits. Inter-
rupt bits automatically latch themselves into their register
locations and assert the nterrupt pin INT ow and nterrupt
bits INT and INT_GLBL high when they change state.
Interrupt bits stay latched until they are read. When
interrupt bits are read, the interrupt register bit INT is
cleared for that register and the interrupt bit is updated to
Sym
Name
Definition
Write Cycle
Input
Read Cycle
No Operation,
Hi Z
Output
W
Write
R
Read
No Operation,
Hi Z
Input
R/W
Read/Write
Ouput
R/W
SC
Read/Write,
Self
Clearing
Input
Output
Clears Itself
After
Operation
Completed
R/LT
Read,
Latching On
Transition
No Operation,
Hi Z
Output
When Bit
Transitions,
Bit Latched
And Interrupt
Set.
When Bit
Is Read,
Interrupt
Cleared And
Bit Updated.
Table 2. Serial Port Register Bit Type Definition
相關PDF資料 |
PDF描述 |
|---|---|
| 84C24 | Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網(wǎng)媒體接口適配器) |
| 84C300A | 84C300A 4-Port Fast Ethernet Controller manual 3/98 |
| 84C30A | 84C30A 10 Mbps Controller (MAC) manual 12/96 |
| 84C300A | 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器) |
| 84CNQ035 | Schottky Rectifier |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 84C2A-A12-J06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J06L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J08L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-J10L | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
| 84C2A-A12-K06 | 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn |
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