參數(shù)資料
型號(hào)： 84C24
英文描述： 84C24 Quad 10BASE-T Ethernet Media Interface Adapter manual 6/96
中文描述： 84C24四10BASE - T以太網(wǎng)媒體接口適配器手冊(cè)6 / 96
文件頁數(shù)： 14/51頁
文件大?。?/td> 435K
代理商： 84C24
84C24
4-14
MD400147/A
3.17 POWERDOWN
The 84C24 can be powered down by setting the power-
down enable bit in the serial port Global Configuration
register. In powerdown mode, the outputs are tristated
and the power consumption is reduced to less than 0.5
mW.
3.18 OSCILLATOR
The 84C24 requires a 10 Mhz reference frequency for
internal signal generation. This 10Mhz reference fre-
quency is generated by either connecting an external
crystal between OSCIN and GND or an external 10 MHz
clock o OSCIN. TXC output s synchronized o he OSCIN
clock Input.
3.19 LED DRIVERS
The PLED[3:0] pins contain an open drain output ransistor
with a resistor pullup. These outputs can drive LED's tied
to V
CC
or other digital inputs.
The PLED[3:0] pins can be programmed to perform one
of five different functions: (1) Link Detect, (2) Full Duplex
Detect, (3) On, (4) Off, or (5) Blink.
The PLED[3:0] pins can be programmed for one of these
5 functions by appropriately setting the LED output select
bits n he Global Configuration and Channel Configuration
registers. When the PLED[3:0] pins are programmed to
indicate Link or Full Duplex, the LED output drivers are
controlled by the internal logic as described in the Link
Integrity and Full Duplex section. When PLED[3:0] are
programmed to be On, the LED output goes low, thus
turning on the LED. When PLED[3:0] s programmed to be
Off, the LED output driver turn off, thus turning off the LED.
When PLED[3:0] is programmed to Blink, the LED output
driver will continuously turn on and turn off at a rate of 100
ms on, 100 ms off.
3.20 SERIAL PORT
3.20.1 Signal Description
The serial port has eight pins: SCLK, SDIO INT, CS and
SA[3:0]. SCLK is the serial shift clock input. SDIO is a
bidirectional data I/O pin. INT is an interrupt output. CS is
a serial port select input. SA[3:0] are address pins for the
serial port.
SA[3:0] share the same pins as the PLED[3:0] output,
drivers respectively. At powerup or reset, the output
drivers are tristated for an interval called the power-on
reset ime. During he power-on reset nterval, he value on
these pins s atched nto the device and used as the serial
port address.
3.20.2 Timing and Multiple Register Access
The serial port is idle when CS=1. During idle, SDIO is in
the high mpedance state. When CS goes ow, a serial shift
cycle s nitiated. Data on SDIO s hen shifted n on he irst
16 falling edges of SCLK (SDIO is high impedance). On
the next 16 falling edges of SCLK, data is either shifted in
or out on SDIO, depending on whether a write cycle or read
cycle was selected with he bit R/W. After he irst 32 SCLK
clock cycles have been completed, one complete register
has been read/written. If CS is still kept low for an
additional 16 SCLK clock cycles, the next register number
in numerical order is accessed and read/written. This
multiple register access can continue on as many registers
as desired as ong as CS continues to stay ow and groups
of 16 SCLK clocks are present. When CS goes high or
when all registers have been accessed in a multiple
register access cycle, the serial shifting process is halted,
the data is latched into the device, and SDIO goes into the
high impedance state.
INT s an output pin that goes ow whenever any one of the
interrupt bits changes state in the serial port Channel
Status registers. After the serial port bit that set the
interrupt is read out, INT is reset back to a high. Refer to
the Interrupt section for more details.
3.20.3 Frame Structure
The structure of the serial port frame is shown in Table 3.
Each serial port access cycle consists of 32 bits, minimum.
The first 16 bits of the serial port cycle are always write bits
and are used for addressing. The last 16+ bits are from
one or more of the ten internal registers.
The first bit in the serial port frame is a start bit and needs
to be written as a 0 for the serial port cycle to continue. The
next bit s a read/write bit which determines f the accessed
register(s) bits will be read or write. The next 8 bits are
device addresses, and PHYAD[7:4] must be 1111 and
PHYAD[3:0] must match the values on pins SA[3:0] for the
serial port access to continue. The next 4 bits are register
address select bits which select one of the ten data
registers for access. The next 2 bits are turnaround bits
which are not actual register bits but extra time for SDIO to
switch from write to read if necessary. The final 16+ bits
of the serial port cycle come from one or more registers
designated by the register address bits.
3.20.4 Bit Types
Since the serial port is bidirectional, there are many
different ype of bits. Write bits (W) are nputs during a write
cycle and are high impedance during a read cycle. Read
bits (R) are outputs during a read cycle and high imped-
ance during a write cycle.Read/Write bits (R/W) are actu-
ally write bits which can be read out during a read cycle.
相關(guān)PDF資料
PDF描述
84C24 Quad 10Base-T Ethernet Media Interface Adapter(四通道10Base-T以太網(wǎng)媒體接口適配器)
84C300A 84C300A 4-Port Fast Ethernet Controller manual 3/98
84C30A 84C30A 10 Mbps Controller (MAC) manual 12/96
84C300A 4-Port Fast Ethernet Controller(四端口快速以太網(wǎng)控制器)
84CNQ035 Schottky Rectifier
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
84C2A-A12-J06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-J06L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-J08L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-J10L 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
84C2A-A12-K06 制造商:BOURNS 制造商全稱:Bourns Electronic Solutions 功能描述:83/84 - 5/8 Square 10-Turn
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