參數(shù)資料
型號: 844256BGT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: 622.08 MHz, OTHER CLOCK GENERATOR, PDSO24
封裝: 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24
文件頁數(shù): 5/17頁
文件大?。?/td> 390K
代理商: 844256BGT
IDT / ICS LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
13
ICS844256BG REV. A NOVEMBER 7, 2008
ICS844256
FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844256.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844256 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (160mA + 20mA) = 623.7mW
Power (outputs)
MAX
= V
DDO_MAX
* I
DDO_MAX
= 3.465V * 160mA = 554.5mW
Total Power
_MAX
= 623.7mW + 554.5mW = 1178.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM devices is 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 1.178W * 32.1°C/W = 107.8°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (multi-layer).
TABLE 7. THERMAL RESISTANCE
θθθθθ
JA
FOR
24-LEAD TSSOP, E-PAD, FORCED CONVECTION
θθθθθ
JA
by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
32.1°C/W
25.5°C/W
24.0°C/W
相關PDF資料
PDF描述
84624-103LF 10 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, PRESS FIT
84624-103 10 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, PRESS FIT
84624-203LF 10 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, PRESS FIT
84624-203 10 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, PRESS FIT
84624-303 10 CONTACT(S), MALE, STRAIGHT TWO PART BOARD CONNECTOR, PRESS FIT
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