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參數(shù)資料
| 型號(hào)： | 844256BGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 622.08 MHz, OTHER CLOCK GENERATOR, PDSO24 |
| 封裝： | 4.40 X 7.80 MM, 0.92 MM HEIGHT, MO-153, TSSOP-24 |
| 文件頁數(shù)： | 2/17頁 |
| 文件大?。?/td> | 390K |
| 代理商： | 844256BGT |
IDT / ICS LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER
10
ICS844256BG REV. A NOVEMBER 7, 2008
ICS844256
FEMTOCLOCKS CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in
Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it
is recommended that the amplitude be reduced from full swing
to half swing in order to prevent signal interference with the
power rail and to reduce noise. This configuration requires that
the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
impedance. For most 50
Ω applications, R1 and R2 can be 100Ω.
This can also be accomplished by removing R1 and making R2
50
Ω.
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTAL_IN
XTAL_OUT
VCC
R2
Ro
R1
Zo = 50
Rs
VCC
.1uf
VDD
Zo = Ro + Rs
Reference Document: JEDEC Publication 95, MO-153
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in
Figure 4. In a 100
Ω
differential transmission line environment, LVDS dr ivers
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
require a matched load termination of 100
Ω across near
the receiver input.
2.5V or 3.3V
+
-
VDD
100 Ohm Differential Transmission Line
R1
100
LVDS_Driv er
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 844256CK-24LF | 制造商:Integrated Device Technology Inc 功能描述:LVDS 0.385V 32PIN VFQFN - Rail/Tube |
| 844256CK-24LFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Synthesizer Single 32-Pin VFQFPN EP T/R 制造商:Integrated Device Technology Inc 功能描述:32 VFQFN (LEAD-FREE) - Tape and Reel |
| 844256DGILF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 844256DGILFT | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| 844256DGLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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