參數(shù)資料
型號: 83PN625DKILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: 625 MHz, OTHER CLOCK GENERATOR, QCC10
封裝: 5 X 7 MM, 1 MM PITCH, ROHS COMPLIANT, VFQFN-10
文件頁數(shù): 4/17頁
文件大?。?/td> 1314K
代理商: 83PN625DKILF
ICS83PN625I Data Sheet
PROGRAMMABLE FEMTOCLOCK NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN625DKI REVISION A MARCH 17, 2010
12
2010 Integrated Device Technology, Inc.
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS83PN625I.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS83PN625I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 131mA = 453.915mW
Power (outputs)MAX = 32mW/Loaded Output pair
Total Power_MAX (3.3V, with all outputs switching) = 453.915mW + 32mW = 485.915mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 39.2°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.486W * 39.2°C/W = 104.1°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 10 Lead VFQFN, Forced Convection
θ
JA vs. Air Flow
Meters per Second
0
Multi-Layer PCB, JEDEC Standard Test Boards
39.2°C/W
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