參數(shù)資料
型號: 83PN625DKILF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: XO, clock
英文描述: 625 MHz, OTHER CLOCK GENERATOR, QCC10
封裝: 5 X 7 MM, 1 MM PITCH, ROHS COMPLIANT, VFQFN-10
文件頁數(shù): 10/17頁
文件大?。?/td> 1314K
代理商: 83PN625DKILF
ICS83PN625I Data Sheet
PROGRAMMABLE FEMTOCLOCK NG LVPECL OSCILLATOR REPLACEMENT
ICS83PN625DKI REVISION A MARCH 17, 2010
2
2010 Integrated Device Technology, Inc.
Table 1. Pin Descriptions
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Function Table
Table 3. Divider Function Table
Number
Name
Type
Description
1
OE
Pullup
Output enable. External pullup required for normal operation.
LVCMOS/LVTTL interface levels.
2
Reserved
Reserve
Reserved pin. Do not connect
3VEE
Power
Negative supply pin.
4,
5
XTAL_OUT
XTAL_IN
Input
Crystal oscillator interface XTAL_IN is the input, XTAL_OUT is the output. This
oscillator interface can also be driven by a single-ended reference clock.
6, 7
Q, nQ
Output
Differential output pair. LVPECL interface levels.
8VCC
Power
Power supply pin.
9
FSEL0
Input
Pullup
Output frequency select pin. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.
10
FSEL1
Input
Pullup
Output frequency select pin. Sets the output divider value to one of four values.
LVCMOS/LVTTL interface levels. See Frequency Select Table on page 1.
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4pF
RPULLUP
Input Pullup Resistor
51
k
FSEL[1:0]
M Value
N Value
0 0
100
÷16
0 1
100
÷4
1 0
80
÷8
1 1 (default)
100
÷8
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