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參數(shù)資料
| 型號(hào)： | 83336-00 |
| 廠商： | Peregrine Semiconductor |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVAL FOR 83336 PLL INTEGER-N |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | UltraCMOS™ |
| 類型： | 整數(shù) N/PLL |
| 頻率： | 3GHz |
| 適用于相關(guān)產(chǎn)品： | PE83336 |
| 已供物品： | 板 |
| 其它名稱： | 83336-0 83336-0-ND PE83336EK |
Product Specification
PE83336
Page 6 of 12
2010-2012 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0137-05 │ UltraCMOS RFIC Solutions
Table 6. AC Characteristics: VDD = 3.0 V, -55° C ≤TA ≤125° C, unless otherwise specified
Note 1: Parameter is guaranteed through characterization only and is not tested.
Note 2: Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a low-
noise amplifier to square up the edges is recommended at lower input frequencies.
Note 3: CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster
than 80mV/ns.
Note 4: All devices are screened to phase noise limits listed in Table 7. The magnitude of the tester uncertainty precludes testing phase noise as
part of qualification testing. These parameters are also exempt from PDA requirements.
Note 5: Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Control Interface and Latches (see Figures 4, 5, 6)
fClk
Serial data clock frequency
10
MHz
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
30
ns
tDSU
Sdata set-up time after Sclk rising edge, D[7:0] set-up
time to M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
10
ns
tPW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
30
ns
tCWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
30
ns
tCE
Sclk falling edge to E_WR transition
30
ns
tWRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
30
ns
tEC
E_WR transition to Sclk rising edge
30
ns
tMDO
MSEL data out delay after Fin rising edge
CL = 12 pf
8 (Note 5)
ns
Main Divider (Including Prescaler)
Fin
Operating frequency
500
3000
MHz
PFin
Input level range
External AC coupling
-5
5
dBm
External AC coupling
85
C < TA ≤125C
0
5
dBm
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
50
300
MHz
PFin
Input level range
External AC coupling
-5
5
dBm
External AC coupling
85
C < TA ≤125C
0
5
dBm
Reference Divider
fr
Operating frequency
(Note 1)
(Note 2)
100
MHz
Pfr
Reference input power
Single ended input
-2
10
dBm
Vfr
Input sensitivity
External AC coupling
(Note 3)
0.5
VP-P
Phase Detector
fc
Comparison frequency
(Note 1)
20
MHz
SSB Phase Noise : Output Referred (Fin = 1918MHz, fr = 10 MHz, fc = 1MHz, LBW = 70 kHz)
PNOR
Output Referred Phase Noise
100 Hz Offset:
VDD = 3.0V, T = 25°C
-78
(Note 4)
dBc/Hz
PNOR
Output Referred Phase Noise
1000 Hz Offset:
VDD = 3.0V, T = 25°C
-84
(Note 4)
dBc/Hz
PNOR
Output Referred Phase Noise
10000 Hz Offset:
VDD = 3.0V, T = 25°C
-87
(Note 4)
dBc/Hz
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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