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參數(shù)資料
| 型號： | 82C931 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Plug and Play Integrated Audio Controller |
| 中文描述： | 即插即用集成音頻控制器 |
| 文件頁數(shù)： | 50/64頁 |
| 文件大?。?/td> | 634K |
| 代理商： | 82C931 |
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82C931
Page 42
912-3000-035
Revision: 2.1
OPTi
CIR10
Pin Control Register
Default = 00h
Reserved
Interrupt pin:
(1)
0 = Disable
1 = Enable
(Interrupt pin
goes active high
when the num-
ber of samples
programmed in
the Base Count
Register is
reached.)
Reserved
2.
In Sound Blaster mode, the software driver should set bit 1 = 1.
CIR11
Error Status and Initialization Register (RO)
Default = 00h
Capture
overrun:
(1)
This bit is set
when capture
data has not
been read by
the host before
the next sam-
ple arrives. The
sample being
read will not be
overwritten by
the new sam-
ple. The new
sample is
ignored.
(1) Bit changes on a sample-by-sample basis.
(2) The occurrence of a capture overrun and/or playback underrun is designated in the Status Register's sample overrun/underrun bit
(WSBase+06h[4]). The sample overrun/underrun bit is the logical OR of bits 7 and 6. This enables a polling host CPU to detect an over-
run/underrun condition while checking other status bits.
Playback
underrun:
(1)
This bit is set
when playback
data has not
arrived from
the host in time
to be played.
This results in a
midscale value
sent to the
DACs.
Autocalibration
state:
0 = In progress
1 = Not in
progress
Current status
of PDRQ and
CDRQ:
0 = Inactive
(low)
1 = Active (high)
Indicates under/over range on
right input channel:
(1)
0 = Less than –1dB under range
1 = Between –1dB and 0dB under
range
2 = Between 0dB and +1dB over
range
3 = Greater than +1dB over range
Indicates under/over range on
left input channel:
(1)
0 = Less than –1dB under range
1 = Between –1dB and 0dB under
range
2 = Between 0dB and +1dB over
range
3 = Greater than +1dB over range
CIR12
ID Register
Default = 0Ah
Reserved
Revision ID (RO):
These bits define the revision level of the codec.
CIR13
Reserved
Default = 00h
CIR14
Playback Upper Base Count Register
Upper Base Count:
Default = 00h
This byte is the upper byte of the base count register containing the eight most significant bits of the 16-bit base register.
Reads from this register return the same value which was written The current count contained in the counters can not be read.
When enabled for SB Mode, this register is used for both the Playback and Capture Base Registers.
Table 5-10
Codec Indirect Registers (cont.)
D7
D6
D5
D4
D3
D2
D1
D0
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| 82-CBSA-1.75X6.0X0.8 | 功能描述:82-CBSA-1.75X6.0X0.8--82S04--CIR 制造商:leader tech inc. 系列:* 零件狀態(tài):在售 類型:屏蔽，分體式 高度 - 總:0.800"（20.32mm） 長度 - 總:6.000"（152.40mm） 寬度 - 總:1.750"（44.45mm） 通風(fēng):通風(fēng)孔，按樣式排列 安裝類型:通孔 標(biāo)準(zhǔn)包裝:50 |
| 82-CBSA-3.75X4.5X0.8 | 功能描述:82-CBSA-3.75X4.5X0.8--82S12--CIR 制造商:leader tech inc. 系列:* 零件狀態(tài):在售 類型:屏蔽，分體式 高度 - 總:0.800"（20.32mm） 長度 - 總:4.500"（114.30mm） 寬度 - 總:3.750"（95.25mm） 通風(fēng):通風(fēng)孔，按樣式排列 安裝類型:通孔 標(biāo)準(zhǔn)包裝:50 |
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