參數(shù)資料
型號(hào)： 82C931
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： Plug and Play Integrated Audio Controller
中文描述： 即插即用集成音頻控制器
文件頁(yè)數(shù)： 42/64頁(yè)
文件大?。?/td> 634K
代理商： 82C931
82C931
Page 34
912-3000-035
Revision: 2.1
OPTi
MCIR19
FM Control Register
Default = xxh
IDE IRQ input
routed to IRQ
output:
0 = Disable
1 = Enable
SDHOE
function on pin
43 when config-
ured for MB
Mode:
0 = Disable
1 = Enable
IRQ3, IRQ4:
0 = Disable
1 = Enable
Reserved
MEGA bass:
0 = Disable
1 = Enable
OPTi mode for
enhanced FM
features:
0 = Disable
1 = Enable
External FM
select:
0 = Disable
1 = Enable
MCIR20
GPIO Control Register 0
Default = 00h
GPIO3
mapping:
0 = Pin 42
931-AD
1 = Pin 36
931-MB
Note:
GPIO3
pin type:
0 = Input
1 = Output
GPIO2
mapping:
0 = Pin 41
931-AD
1 = Pin 35
931-MB
GPIO2
pin type:
0 = Input
1 = Output
GPIO1
mapping:
Pin 11 for
931-AD and
931-MB
GPIO1
pin type:
0 = Input
1 = Output
GPIO0
mapping:
Pin 43 for
931-AD and
931-MB
GPIO0
pin type:
0 = Input
1 = Output
GPIO function is available only when the specified pin is not being used for another function.
MCIR21
Serial Audio Control Register 0
Default = 00h
CTL_SEL[1:0]
ASIO shift clock selection
00/11 = Use the shift clock from
internal FS
01 = Use FM timing
10 = Use external SCLK
P2S_SEL[1:0]
SAO data source selection
00/11 = From DMA Playback
01 = From FM
10 = From ADC, captured from
analog section
SPCDSEL
Enables dual
playback
0 = 2nd DMA
channel is used
for DMA cap-
ture
1 = 2nd DMA is
used with 1st
DMA channel
for DMA play-
back
ADCSEL
Selects DMA
data capture
source
0 = ADC data
(from analog
section)
1 = SAI data
FDACSEL
Selects FDAC
data source
0 = FDAC
takes FM data
1 = FDAC
takes SADI (if
SPCDSEL=0),
2nd DMA play-
back data (if
SPCDSEL=1)
DACSEL
Selects DAC
data souce
0 = DMA play-
back
1 = SAI
MCIR22
Serial Audio Control Register 1
Default = 00h
Reset
ASIO:
0 = Normal
1 = Reset
ASIO test
mode:
0 = Normal
1 = Test
F16
Specify ASIO
sample period
data location:
0 = Last 16 bits
of the L/R half
sample period
1 = First 16/17
bits of L/R half
sample period
CLK32
Number of
SLCKs in a
sample period
(delay-mode or
pulse-mode
ASIO only)
0 = 32
1 = >32
SCLK
polarity:
0 = Reverse
1 = No changed
FSYNC
polarity:
0 = Reverse
1 = No changed
PULSE
Pulse mode
type of serial
data
(AT&T7525
comp or
CS8412 DSP)
0 = Not acti-
vated
1 = Activated
Table 5-6
MC Indirect Registers (cont.)
7
6
5
4
3
2
1
0
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